Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
144 of 366
10.14 Bit Error Rate Test Functions (BERTs)
10.14.1 BERT General Description
The BERT (Bit Error Rate Tester) is a software-programmable test-pattern generator and monitor capable of
meeting most error performance monitoring requirements for digital transmission equipment. It is used to test and
stress communication links. Each E1/T1 transceiver has its own dedicated BERT circuitry.
The BERT can generate and synchronize to pseudo-random patterns with a generation polynomial of the form x
n
+
x
y
+ 1 and to repetitive patterns of any length up to 32 bits. The pattern generator (Tx BERT) generates the
programmable test pattern, and inserts the test pattern into the data stream. The pattern detector (Rx BERT)
extracts the test pattern from the Rx data stream and monitors it. Figure 6-1
shows the location of the BERT blocks
in E1/T1 transceiver circuitry.
10.14.2 BERT Features
 Programmable PRBS pattern – The Pseudo Random Bit Sequence (PRBS) polynomial (x
n
+ x
y
+ 1) and
seed are programmable (length n = 1 to 32, tap y = 1 to n - 1, and seed = 0 to 2
n
- 1).
 Programmable repetitive pattern – The repetitive pattern length and pattern are programmable (length n
= 1 to 32 and pattern = 0 to 2
n
- 1).
 24-bit error count and 32-bit bit count registers
 Programmable bit error insertion – Errors can be inserted individually or at a specific rate. The rate 1/10
n
is programmable (n = 1 to 7).
 Pattern synchronization at a 10
-3
BER – The Rx BERT can synchronization with the pattern in the
incoming data stream even in the presence of a bit error rate (BER) as high as 10
-3
.
10.14.3 BERT Configuration and Monitoring
The configuration and status registers related to the BERT block are shown in the following table:
Register Name Description
Functions Page
Global Registers
GCR2 Global Control Register 2 global counter update (BRPMU) 153
GTISR Global Transceiver Interrupt Status Register Per-BERT interrupt status bits (BISn) 154
GTIMR Global Transceiver Interrupt Mask Register Per-BERT interrupt mask bits (BIMn) 155
Framer Registers
RXPC Rx Expansion Port Control Register Rx BERT enable, direction, un/framed 252
RBPBS Rx BERT Port Bit Suppress Register Rx bit suppression within the DS0 253
RBPCS1-4 Rx BERT Port Channel Select Registers Rx DS0 channel selection 271
TXPC Transmit Expansion Port Control Register Tx BERT enable, direction, un/framed 294
TBPBS Transmit BERT Port Bit Suppress Register Tx bit suppression within the DS0 295
TBPCS1-4 Transmit BERT Port Channel Select Registers Tx DS0 channel selection 303
BERT Registers
BCR BERT Control Register pattern load, invert, counter update 313
BPCR BERT Pattern Configuration Register pattern type, length, feedback, QRSS 314
BSPR1 BERT Seed/Pattern Register 1 32-bit pattern seed value 315
BSPR2 BERT Seed/Pattern Register 2 32-bit pattern seed value 315
TEICR Transmit Error Insertion Control Register error insertion, single or specified rate 316
BSR BERT Status Register bit error detected, out of sync 316
BSRL BERT Status Register Latched latched status, can cause interrupts 317
BSRIE BERT Status Register Interrupt Enable interrupt mask bits 317
RBECR1 Rx Bit Error Count Register 1 24-bit error count 318
RBECR2 Rx Bit Error Count Register 2 24-bit error count 318
RBCR1 Rx Bit Count Register 1 32-bit total bit count 319
RBCR2 Rx Bit Count Register 2 32-bit total bit count 319