Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
139 of 366
incoming signal to recover clock and data. The receiver has excellent jitter tolerance as shown in Figure 10-72 a
nd
Figure 10-73.
Figure 10-72. Jitter Tolerance, T1 Mode
Figure 10-73. Jitter Tolerance, E1 and 2048kHz Modes
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 or T1 signal on the
RTIP/RRING
inputs. If the jitter attenuator is placed in the Rx path (LTRCR.JAPS=01), the jitter attenuator restores
the RCLK to approximately 50% duty cycle. If the jitter attenuator is placed in the transmit path or is disabled, the
RCLK output can exhibit slightly less than 50% duty cycle. This is due to the highly over-sampled digital clock
recovery circuitry. When no signal is present at RTIP/RRING,
a Rx loss of signal condition occurs (LRSR.LOS=1)
and the RCLK signal is derived from either the E1CLK or T1CLK signal.
UNIT INTERVALS (UIpp)
FREQUENCY (Hz)
1K
100
10
1
0.1
10 100 1k 10k 100k
DS3100 Jitter
Tolerance
1
TR 62411 (Dec. 90)
ITU-T G.823
FREQUENCY (Hz)
UNIT INTERVALS (UIpp)
1k
100
10
1
0.1
10 100 1k 10k 100k
DS3100 Jitter
Tolerance
1
Minimum Tolerance
Level as per
ITU G.823
40
1.5
0.2
20
2.4k
18k