Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name Description Functions Page
RHPBA Rx HDLC Packet Bytes Available Register Rx real-time byte in FIFO status 269
RHF Rx HDLC FIFO Register Rx FIFO read register 270
RRTS5 Rx Real-Time Status Register 5 Rx FIFO fill and packet status 269
RLS5 Rx Latched Status Register 5 Rx FIFO and packet latched status 257
RIM5 Rx Interrupt Mask 5 Rx interrupt mask bits 263
THC1
Transmit HDLC Control 1
Tx HDLC configuration bits 275
THBSE Transmit HDLC Bit Suppress Tx bit suppress within the channel 276
THC2 Transmit HDLC Control 2 Tx HDLC mapping to DS0, etc. 277
THFC Transmit HDLC FIFO Control Tx FIFO low water mark 294
TRTS2 Transmit HDLC Status Tx FIFO fill and packet status 300
TLS2 Transmit HDLC Latched Status Tx FIFO and packet latched status 297
TIM2 Transmit Interrupt Mask Register 2 Tx interrupt mask bits 299
TFBA Transmit HDLC FIFO Buffer Available Tx real-time buffer available status 301
THF Transmit HDLC FIFO Tx FIFO write register 301
10.12.1 Receive HDLC Controller
The receive HDLC controller is always enabled. A low-to-high transition on RHC.RHR resets the receive HDLC
controller and flushes the receive HDLC FIFO. In T1 ESF mode, the receive HDLC controller can be connected to
the FDL (RHC.RHMS=1)
or to any DS0 channel (RHMS=0). In E1 mode, it can be connected to an Sa bit channel
(RHMS=1) or to any DS0 channel (RHMS=0). The RHC.RHCS
field specifies the DS0 channel when RHMS=0.
When RHC.RCRCD=1, the
received CRC-16 (the frame check sequence or FCS) is written to the FIFO after the
last byte of the packet. When RCRCD=0, the CRC-16 is not written to the FIFO. When the receive HDLC controller
is connected to a DS0 channel, it can be configured to look at or ignore individual bit positions of the DS0 channel
by setting the bit fields of the RHBSE re
gister appropriately.
The CPU can read the receive HDLC FIFO one byte at a time by reading the RHF re
gister. When the receive
FIFO’s fill status transitions from empty to not-empty, RLS5.RNES is set to one to inform the CPU that so
mething is
available to be read from the receive FIFO. The lower seven bits of the RHPBA regis
ter (RPBA[6:0]) are a real-time
field that indicates the number of bytes available to be read from the receive FIFO. The MSb of RHPBA (th
e
message status bit, MS) indicates whether the bytes indicated by the RPBA field are the end of a message or not.
The CPU must take into account the value of the RHPBA.RPB
A field when reading the FIFO to prevent FIFO
underrun. There is no underrun indication available from the Rx HDLC controller.
If software reads the FIFO more slowly than the Rx HDLC controller writes it, the fill level of the FIFO rises. When
the HDLC fills above the receive high watermark set in RHFC.RFHWM, the RLS5.RHWMS lat
ched status bit is set.
If the FIFO overruns, the current packet being processed is dropped, the FIFO is emptied, and the latched status
bit RLS5.ROVR is
set to indicate the overrun.
The real-time status bits in RRTS5
and the latched status bits in RLS5 plus the message status bit (MS) in RHPBA
provide message delineation information to the system. In RRTS5
the packet status field PS[2:0] indicates the real-
time status of the packet currently being received: in-progress, OK (i.e. ended without error), CRC error, aborted,
terminated because of overrun. In RLS5, the
RHOBT latched status bit indicates when the next byte available in
the FIFO is the first byte of a message, while the RPS and RPE bits indicate that the Rx HDLC controller has
detected the start of packet or the end of a packet, respectively.
The latched status bits in RLS5 cau
se interrupt requests if enabled by the associated interrupt enable bits in RIM5.
10.12.1.1 Receive HDLC Controller Example
The receive HDLC controller status and control fields provide flexibility to support various software implementations
for receive HDLC servicing. Polling, interrupt-driven or combination approaches are all feasible. A flowchart of an
example receive HDLC servicing routine is shown in Figure 10-66 below.