Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name Description Functions Page
TLS1 Transmit Latched Status Register 1 Tx SLC-96 multiframe alignment event 296
RCR2-T1 Receive Control Register 2 Rx SLC-96 enable control bit 229
RSLC Receive SLC-96 Data Link Registers 1 to 3 Rx SLC-96 overhead values 238
RLS7 Receive Latched Status Register 7 Rx SLC-96 multiframe alignment event 258
10.11.16.1 Transmit SLC–96
The TFDL register is used to insert the SLC-96 message fields. To insert the SLC-96 message using the TFDL
register, the system should configure the transmit formatter as follows:
 TCR2-T1.TS
LC96 = 1 Enable Transmit SLC-96
 TCR2-T1.TFDLS =
0 Source Fs bits via TFDL or SLC-96 formatter
 TCR3.TFM =
1 SF (D4) framing Mode
 TCR1-T1.TF
PT = 0 Do not pass through TSER F-bits.
With these settings, the transmit formatter automatically inserts the 12-bit alignment pattern in the Fs bits for the
SLC-96 data link frame. Data from the TSLC
registers is inserted into the remaining Fs bit locations of the SLC-96
multiframe. The status bit TLS1.TSLC9
6 is set to indicate that the SLC-96 data link buffer has been transmitted and
that the user should write new message data into the TSLC re
gisters. The CPU has 9ms after the assertion of
TLS1.TSLC96 to write the TSLC re
gisters as needed. If no new data is provided in these registers, the previous
values are retransmitted.
10.11.16.2 Receive SLC–96
To enable the receive framer to synchronize onto a SLC–96 pattern, the system should configure the receive
framer as follows:
 RCR1-T1.RFM = 1 SF (D4) framing mode
 RCR1-T1.SYNCC = 1 Set to cross-couple Ft and Fs bits
 RCR2-T1RS
LC96 = 1 Enable SLC-96 synchronizer
 RCR1-T1.SYNCT = 0 Set to minimum sync time
The received SLC–96 message bits can be read from the RSLC re
gisters. The RLS7-T1.RSLC96 status bit is
useful for retrieving SLC-96 message data. The RSLC96 bit indicates when the framer has updated the RSLC
regi
sters with the latest message data from the incoming data stream. After the RSLC96 bit is set, the CPU has
9ms (i.e. until the next RSLC96 interrupt) to retrieve the most recent message data from the RSLC regi
sters. Note
that RSLC96 is not set if the framer is unable to detect the 12-bit SLC-96 alignment pattern.
10.12 HDLC Controllers
This device has an enhanced HDLC controller that can be mapped into a single timeslot, or the T1 FDL or one of
the E1 Sa4 to Sa8 bits. When mapped to a timeslot, the HDLC controller can be configured to use all or only a
subset of the bits of the timeslot.
The HDLC controller performs all the necessary overhead for generating and receiving Performance Report
Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC
controller automatically generates and detects flags, generates and checks the CRC checksum, generates and
detects abort sequences, stuffs and de-stuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the
HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention. The
registers related to the HDLC are displayed in the following table.
Register Name Description Functions Page
RHC Rx HDLC Control Register Rx HDLC mapping to DS0 or FDL 227
RHBSE Rx HDLC Bit Suppress Register Rx bit suppress within the channel 228
RHFC Rx HDLC FIFO Control Rx FIFO high water mark 251