Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
128 of 366
Table 10-57. Registers Related to T1 In-Band Loop Code Detection
Register Field Description Functions Page
RIBCC Rx In-Band Code Control Register Rx up code and down code length 247
RUPCD1 Rx Up Code Definition Register 1 Rx up code definition 265
RUPCD2 Rx Up Code Definition Register 1 Rx up code definition 266
RDNCD1 Rx Down Code Definition Register 1 Rx down code definition 266
RDNCD2 Rx Down Code Definition Register 2 Rx down code definition 267
RSCC Rx In-Band Spare Control Register Rx spare code length 252
RSCD1 Rx Spare Code Register 1 Rx spare code register 259
RSCD2 Rx Spare Code Register 1 Rx spare code register 259
RRTS3-T1 Rx Real-Time Status Register 3 real-time loop/spare code detect bits 268
RLS3-T1 Rx Latched Status Register 3 latched loop/spare code detect bits 255
RIM3-T1 Rx Interrupt Mask Register 3 interrupt mask bits 261
10.11.15 G.706 Intermediate CRC-4 Recalculation (E1 Only)
The framer can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled,
the data stream presented at TSER already has the FAS/NFAS, CRC-4 multiframe alignment word and CRC-4
checksum in timeslot 0. The CPU can modify the Sa bit positions and this change in data content can then be used
to modify the CRC-4 checksum. This modification, however, does not corrupt any error information the original
CRC-4 checksum may contain. In this mode of operation, TSYNC must be configured to multiframe mode
(TIOCR.TSM
=1). The data at TSER must be aligned to the TSYNC signal. If TSYNC is an input then the system
must assert TSYNC aligned at the beginning of the multiframe relative to TSER. If TSYNC is an output, the system
must multiframe-align the data presented to TSER. This mode is enabled when TCR3.CRC4R=1. Note t
hat the E1
transmitter must already be configured for CRC insertion with TCR1-E1.T
CRC4=1.
Figure 10-65. CRC-4 Recalculate Method
10.11.16 SLC–96 Operation (T1 Only)
In a SLC-96 transmission scheme, the standard Fs bit pattern is robbed to make room for a set of message fields.
The SLC-96 multiframe is made up of six D4 superframes and is therefore 72 frames long. In the 72-frame
SLC–96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into alarm,
maintenance, spoiler, and concentrator bits as well as 12 bits of the normal Fs pattern. Additional SLC-96
information can be found in Bellcore document TR-TSY-000008. Registers related to SLC-96 functionality are
shown in the following table.
Table 10-58. Registers Related to SLC96
Register Name Description Functions Page
TFDL Transmit FDL Register Tx SLC-96 messages in Ft/Fs bits 280
TSLC Receive SLC 96 Data Link Registers 1 to 3 Tx SLC-96 overhead values 280
TCR2-T1 Transmit Control Register 2 Tx SLC-96 enable control bit 288
DATA
TSER
XOR
CRC-4
CALCULATOR
EXTRACT
OLD CRC-4
CODE
INSERT
NEW CRC-4
CODE
MODIFY
Sa BIT
POSITIONS
NEW Sa BIT
+
POS/NEG
TO LIU