Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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When automatic remote alarm (RAI) generation is enabled (TCR2-E1.ARA=1
), if the receive framer detects any of
the following conditions then the transmit formatter automatically transmits RAI: Rx loss of signal, Rx loss of frame
synchronization, Rx AIS alarm or CRC-4 multiframe synchronization cannot be found within 128ms of FAS
synchronization (if CRC-4 is enabled). RAI generation conforms to ETS 300 011 and ITU G.706 specifications.
Note: It is an illegal state to have both automatic AIS generation and automatic remote alarm generation enabled at
the same time.
10.11.8 Error Count Registers
The receive framer has four internal 16-bit counters that are used to accumulate line coding errors, path errors, and
frames out of sync, and far end block errors (FEBE). The values of these counters can be latched into
corresponding counter registers to be read by the CPU. Update options for the counter registers include one
second boundaries, 42ms (T1 mode only), 62.5ms (E1 mode only) or manually. When ERCNT.EAMS=0, update
s
are automatic, and ERCNT.ECUS sp
ecifies the update period. When ERCNT.EAMS=0, updates are manual. If
ERCNT.MCUS=0, upd
ates are triggered manually by a low-to-high transition on ERCNT.MECU. If
ERCNT.MCUS=1, update
s are triggered manually by a low-to-high transition global configuration bit
GCR1.GF
CLE. The GFCLE bit can be used to simultaneously trigger updates in multiple framers at the same time.
The four counters and their associated count registers are described in the subsections that follow.
10.11.8.1 Line Code Violation Counter and Count Registers
Either bipolar violations or code violations can be counted and reported in the LCVCR registers. Bipolar violations
are defined as consecutive marks of the same polarity. In T1 mode, if the B8ZS decoding is enabled in framer, then
BPVs in B8ZS codewords are not counted. In E1 mode, if HDB3 decoding is enabled in the framer then BPVs in
HDB3 codewords are not counted. If ERCNT.L
CVCRF=1, then code violations are counted as defined in ITU
O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the
framer should be configured to count BPVs when receiving AMI code and to count CVs when receiving B8ZS- or
HDB3-encoded data. This counter increments at all times and is not disabled by loss of frame conditions. The
counter saturates at 65,535 and does not rollover. The bit error rate on an E1 line would have to be greater than
10E-2 before this counter would saturate. See the following tables for details of exactly what this register counts in
different modes.
Table 10-50. T1 Line Code Violation Counting Options
COUNT EXCESSIVE
ZEROS? (ERCNT.L
CVCRF)
B8ZS ENABLED?
(RCR1-T1.RB8ZS) WHAT IS COUNTED IN THE LCVCR REGISTERS
0 0 BPVs
1 0
BPVs + occurrences of 16 consecutive zeroes
0 1 BPVs (but BPVs in B8ZS codewords not counted)
1 1
BPVs + occurrences of 8 consecutive zeros
Table 10-51. E1 Line Code Violation Counting Options
E1 CODE VIOLATION
SELECT (ERCNT.L
CVCRF)
HDB3 ENABLED?
(RCR1-E1.
RHDB3)
WHAT IS COUNTED IN THE LCVCR REGISTERS
0 0 BPVs
0 1 BPVs (but BPVs in HDB3 codewords not counted)
1 don’t care CVs
10.11.8.2 Path Code Violation Counter and Count Registers
In T1 mode, Ft, Fs, or CRC-6 errors can be counted and reported in the PCVCR registers. In T1 SF mode, if
ERCNT.FSB
E=0, only errors in the Ft bit positions are counted. If ERCNT.FSBE=1, errors in both the Ft and Fs bit
positions are counted. In T1 ESF mode, only errors in the CRC-6 codewords are counted. The counter stops
counting during loss of frame conditions (RRTS1.RLOF=1). Table 10-52
summarizes which errors are counted in
each T1 mode of operation.