Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
121 of 366
10.11.5.3
Sa Bit Monitoring and Reporting
In addition to the registers outlined above, the framer provides status and interrupt capability in order to detect
changes in the state of selected Sa bits. The RSAIMR re
gister can be used to select which Sa bits are monitored
for a change of state. When a change of state is detected in one of the enabled Sa bit positions, the
2RLS7-
E1.SaXCD status bit is set. If multiple Sa bits have been enabled, the user can read the SaBITS re
gister to
determine the current value of each Sa bit.
For the Sa6 bits, additional support is available to detect specific codewords per ETSI ETS 300 233. The
Sa6CODE
register reports the received Sa6 codeword. The codeword must be stable for a period of 3 sub-
multiframes and different from the previous stored value in order to be stored in the Sa6CODE regi
ster. Latched
status bit
2RLS7-E1.Sa6CD indicates if the received Sa6 codeword has changed.
10.11.6
Maintenance and Alarms
The receive framer and transmit formatter provides extensive functions for alarm detection and generation,
performance monitoring, and transmission of diagnostic information, including:
Real-time status bits, latched status bits and interrupt mask bits
LOS detection
RAI detection and generation
AIS detection and generation
Pulse density violation detection
Error counters
DS0 monitoring
Milliwatt code generation and detection
Rx and Tx Slip buffer status
Some of the registers related to maintenance and alarms are as follows:
Table 10-46. Registers Related to Maintenance and Alarms
Register Name Description Functions Page
RRTS1 Rx Real-Time Status Register 1 Rx real-time RAI, AIS, LOS, LOF 267
RRTS3-T1 Rx Real-Time Status Register 3 (T1 Mode) Rx up/down/spare code detect 268
RRTS3-E1 Rx Real-Time Status Register 3 (E1 Mode) Rx V5.2 link, remote MF alarm 268
RLS1 Rx Latched Status Register 1 Rx latched RAI, AIS, LOF, LOF set/clr 253
RLS2-T1 Rx Latched Status Register 2 (T1 Mode) Rx pulse density, COFA, F-bit error etc 254
RLS2-E1 Rx Latched Status Register 2 (E1 Mode) Rx FAS/CAS/CRC-4 out of sync 254
RLS3-T1 Rx Latched Status Register 3 (T1 Mode) Rx code detect, loss of Rx clock 255
RLS3-E1 Rx Latched Status Register 3 (E1 Mode) Rx V5.2 link, remote MF alarm 256
RLS4 Rx Latched Status Register 4 Rx signaling change, 1-sec timer, etc. 257
RLS7-T1 Rx Latched Status Register 7 (T1 Mode) Rx RAI-CI, AIS-CI, etc. 258
RLS7-E1 Rx Latched Status Register 7 (E1 Mode) Rx Sa6 code, Sa-bit change 258
RIM1 Rx Interrupt Mask Register 1 interrupt mask bits for RLS1 260
RIM3-T1 Rx Interrupt Mask Register 3 (T1 Mode) interrupt mask bits for RLS3-T1 261
RIM3-E1 Rx Interrupt Mask Register 3 (E1 Mode) interrupt mask bits for RLS3-E1 262
RIM4 Rx Interrupt Mask Register 4 interrupt mask bits for RLS4 263
RIM7-T1 Rx Interrupt Mask Register 7 (T1 Mode) interrupt mask bits for RLS7-T1 264
RIM7-E1 Rx Interrupt Mask Register 7 (E1 Mode) interrupt mask bits for RLS7-E1 265
ERCNT Rx Error Count Configuration Register Configuration of the Error Counters 250
LCVCR1, LCVCR2 Rx Line Code Violation Count Registers 16-bit Rx line code violation counter 234
PCVCR1, PCVCR2 Rx Path Code Violation Count Registers 16-bit Rx path code violation counter 234
FOSCR1, FOSCR2 Rx Frames Out-of-Sync Count Registers 16-bit frame out-of-sync counter 235
EBCR1, EBCR2 Rx E-Bit Count Registers 16-bit E-bit count register 235
TLS1 Tx Latched Status Register 1 loss of Tx clock, Tx pulse density 296
TLS3 Tx Latched Status Register 3 loss of frame alignment 297
TIM1 Tx Interrupt Mask Register 1 interrupt mask bits for TLS1 296
TIM3 Tx Interrupt Mask Register 3 interrupt mask bits for TLS3 297