Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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in RIM7-T1. The CP
U has 2ms (8 * 2 * 125s) to read the data from RFDL before it is lost. Note that in this mode,
no zero stuffing is applied to the FDL data. It is strongly suggested that the HDLC controller be used for FDL
messaging applications.
In the SF framing mode, the framer writes the received Fs framing pattern into the lower six bits of the RFDL
regi
ster, and RLS7-T1.RF
DLF is set every 1.5ms (12 * 125s).
10.11.5 E1 Datalink
The registers related to E1 datalink are shown in the following table:
Register Name Description Functions Page
RAF Receive Align Frame Register Rx first byte of the align frame: Si, FAS 238
RNAF Receive Non-Align Frame Register Rx first byte of the non-align frame 239
RSiAF Receive Si Bits of the Align Frames Rx align-frame Si bits 239
RSiNAF Receive Si Bits of the Non-Align Frames Rx non-align-frame Si bits 240
RSa4 to RSa8 Receive Sa Bits Rx Sa4-Sa8 bits 241
RSAIMR Sa Bit Interrupt Mask Register interrupt masks for Sa bit changes 2230
SaBITS Received Sa Bits last received Sa bit values 243
Sa6CODE Received Sa6 Codeword last validated Sa6 codeword 244
TAF Transmit Align Frame Register Tx first byte of the align frame: Si, FAS 281
TNAF Transmit Non-Align Frame Register Tx first byte of the non-align frame 281
TSiAF Transmit Si Bits of the Align Frame Tx align-frame Si bits 282
TSiNAF Transmit Si Bits of the Non-Align Frames Tx non-align-frame Si bits 282
TSa4 to TSa8 Transmit Sa4 to Sa8 Tx Sa4-Sa8 bits 283
TSACR Transmit Sa Bit Control Register Tx source control bits for Si, RA, SaX 277
The framer, when operated in the E1 mode, provides two methods for accessing the Sa and the Si bits, which are
the two common channels over which a datalink can be run. The first method involves writing/reading data every
E1 double-frame (250s) while the second one involves writing/reading data every CRC-4 multiframe (2ms).
10.11.5.1 Per Double-Frame Access (Method 1)
On the receive side, the RAF and RNAF registers always report the contents of the first eight bits of the align frame
and the non-align frame, respectively, which includes the Si and Sa bits Both registers are updated at the start of
the align frame, which is indicated by the RLS2-E1.RAF
status bit. After RAF is set to 1, software has 250s to
read the registers before they are overwritten by the bits from the next double-frame.
On the transmit side, the TAF and
TNAF registers can source the first eight bits of the align frame and the non-
align frame, respectively. Data is sampled from these registers at the start of the align frame, which is indicated by
the TLS1.TAF s
tatus bit. After TAF is set to 1, software has 250s to update the registers with new values (if
needed) before they are sampled again for the next double-frame. TAF an
d TNAF are the default sources for the
FAS, Si, RAI and Sa bits. However, various control fields can cause some of these bits to be sourced from
elsewhere.
10.11.5.2 Per CRC-4 Multiframe Access (Method 2)
On the receive side, the eight registers RSiAF, RSiNAF, RRA, and RSa4 through RSa8 report the corresponding
overhead bits of the CRC-4 multiframe as they are received. These registers are updated at the start of the next
CRC-4 multiframe, which is indicated by the RLS2-E1.RCMF s
tatus bit. After RCMF is set to 1, software has 2ms
to read the registers before they are overwritten by the bits from the next multiframe.
On the transmit side, the eight registers TSiAF, TSiNAF, TRA, an
d TSa4 through TSa8 can source the
corresponding overhead bits of the multiframe. The control bits in the TSACR re
gister enable the sourcing of
Si/RAI/Sa bits from these registers. Data is sampled from these registers at the start of the multiframe, which is
indicated by the TLS1.TM
F status bit. After TMF is set to 1, software has 2ms to update the registers (if needed)
before they are sampled again for the next multiframe.