Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Glossary
BERT – Bit Error Rate Tester, a function used to test the integrity of a data link. A two-block set consisting of a Tx
BERT that generates pseudo-random or repetitive patterns and optionally inserts bit errors into the sequence, and
an Rx BERT that synchronizes to an incoming pattern and count bit errors.
bundle – a virtual path configured at two endpoint TDMoP gateways to carry TDM or constant bit-rate data over a
PSN.
CLAD – Clock Rate Adapter, an analog PLL that creates an output clock signal that is phase/frequency locked to
an input clock signal of a different frequency. A CLAD is said to “convert” one frequency to another or “adapt”
(change) a clock’s rate to be a frequency that is useful to some other block on the chip.
dword – a 32-bit (4-byte) unit of information (also known as a doubleword)
framer – (1) a digital block that finds E1/T1 frame alignment in an incoming serial data stream and provides various
types of status and alarm information about the signaling including loss-of-signal, loss-of-frame, frame bit errors,
etc. Also known as a receive framer. (2) The word framer is also used generically to stand for the bidirectional
block composed of a receive framer and a transmit formatter.
formatter – a digital block that generates a serial data stream composed of successive E1/T1 frames (and
optionally multiframes) filled with TDM data provided by the system. Also known as a transmit formatter.
transceiver – a transmitter/receiver, which for E1/T1 typically means a block containing a receive framer, a
transmit formatter, an LIU receiver and an LIU transmitter. E.g., DS34T108 has eight built-in E1/T1 transceivers.