Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Table 10-43. Registers Related to T1 Receive BOC
Register Name Description Functions Page
RBOCC Receive BOC Control Register reset and filter/disintegration settings 231
RBOC Receive Bit Oriented Code Register received BOC message 238
RLS7-T1 Receive Latched Status Register 7 BOC detected, cleared latched status 258
RIM7-T1 Receive Interrupt Mask Register 7 interrupt mask bits 264
In T1 ESF mode, the receive framer continuously monitors the FDL bits for a valid BOC message. The BOC detect
status bit RLS7-T1.BD i
s set after a valid message has been detected for a time specified by the receive BOC filter
bits RBOCC.RBF[1:0]. The 6-bit BOC messag
e is then available to be read from the RBOC register. After the CPU
clears the BD bit, it remain clears until a new BOC is detected (or the same BOC is detected following a BOC clear
event). The BOC clear status bit RLS7-T1.B
C is set when a valid BOC is no longer being detected for a time
specified by the receive BOC disintegration bits RBOCC.
RBD[1:0]. The BD and BC status bits can cause an
interrupt request if enabled by the associated interrupt mask bits in the RIM7-T1 registe
r.
10.11.4.3
Legacy T1 Transmit FDL
Note: For most applications, BOC controllers or HDLC controllers in the framer and formatter are better tools for
communication over the FDL than the TFDL an
d RFDL registers. The registers related to transmitting over the FDL
using the TFDL re
gister are listed in the table below.
Table 10-44. Registers Related to Legacy T1 Transmit FDL
Register Name Description Functions Page
TFDL Transmit FDL Register 8 bits of FDL data to transmit 280
TCR2-T1 Transmit Control Register 2 source of Tx FDL bits 288
TLS2 Transmit Latched Status Register 2 transmit FDL empty bit (TFDLE) 297
TIM2 Transmit Interrupt Mask Register 2 interrupt mask bit for TFDLE bit 299
When enabled with TCR2-T1.TFDLS=
0, the transmit formatter sources the FDL (in the ESF framing mode) or the
Fs bits (in the SF framing mode) from the transmit FDL register (TFDL). The L
Sb is transmitted first. After all eight
bits have been shifted out of TFDL, the formatter
sets TLS2.TFDLE=1 to inform the CPU that the buffer is empty
and that more data is needed. TFDLE can cause an interrupt request if enabled by the corresponding interrupt
mask bit in TIM2. The
CPU has 2ms (8 * 2 * 125s) to update TFDL with a new value. If it is not updated, the old
value is transmitted again. Note that in this mode, no zero stuffing is applied to the FDL data. It is strongly
suggested that the HDLC controller be used for FDL messaging applications.
In the SF framing mode, the formatter sources the Fs framing pattern from the lower six bits of the TFDL regi
ster,
and TLS2.TF
DLE is set every 1.5ms (12 * 125s). For the standard framing pattern, TFDL must be set to 0x1C and
TCR2-T1.TFDLS s
hould be set to zero.
10.11.4.4
Legacy T1 Receive FDL
Note: For most applications, BOC controllers or HDLC controllers in the framer and formatter are better tools for
communication over the FDL than the TFDL and RFDL
registers. The registers related to receiving data from the
FDL using the RFDL re
gister are listed in the table below.
Table 10-45. Registers Related to Legacy T1 Receive FDL
Register Name Description Functions Page
RFDL Receive FDL Register 8 bits of received FDL data 237
RLS7-T1 Receive Latched Status Register 7 receive FDL full bit (TFDLF) 258
RIM7-T1 Receive Interrupt Mask Register 7 interrupt mask bit for RFDLF bit 264
In the receive section, the recovered FDL bits or Fs bits are always shifted one-by-one into the receive FDL register
(RFDL). The
LSb is the first bit received. Since RFDL is 8 bits in length, it fills up every 2ms (8 * 2 * 125s). After
all eight bits have been shifted into RFDL, the framer
sets RLS7-T1.RFDLF=1 to inform the CPU that the buffer is
full and needs to be read. RFDLF can cause an interrupt request if enabled by the corresponding interrupt mask bit