Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Table 10-40. Registers Related to Signaling
Register Name Description Functions Page
TS1 - TS16 Tx Signaling Registers 1 to 16 Tx ABCD signaling to be inserted 279
TSSIE1 - TSSIE4 Tx Signaling Insertion Enable Registers 1 to 4 Tx per-channel SW sig. insert controls 278
THSCS1 - THSCS4 Tx Hardware Signaling Channel Select 1 to 4 Tx per-channel HW sig. insert controls 302
RSIGC Rx Signaling Control Register Rx auto and manual signaling freeze 229
RSAOI1 - RSAOI3 Rx Signaling All-Ones Insertion Registers 1 to 3 Rx per-channel sig. all-1s insertion 232
RS1 - RS16 Rx Signaling Registers 1 to 16 Rx ABCD signaling bits received 233
RSS1 - RSS4 Rx Signaling Status Registers 1 to 4 Rx per-channel sig. change status 259
RSCSE1 - RSCSE4 Rx Signaling Change of State Enable 1 to 4 Rx per-channel sig. interrupt enables 265
RLS4 Rx Latched Status Register 4 Rx top-level sig. change latched status 257
RIM4 Rx Interrupt Mask Register 4 Rx top-level sig. change interrupt mask 263
RSI1 – RSI4 Rx Signaling Reinsertion Registers 1 to 4 Rx per-channel reinsertion control 270
10.11.3.1 Transmit Signaling Operation
There are two methods to provide transmit signaling data: software (i.e. from the TS registers) and hardware (i.e.
from the formatter’s TSIG input). Both methods may be used simultaneously. The methods are described in the
subsections below.
10.11.3.1.1 Software Signaling
In the software signaling method, signaling data is loaded into the transmit signaling registers (TS1 - TS16) by the
CPU. Each transmit signaling register contains the signaling bits for two DS0 timeslots. On multiframe boundaries,
the signaling bits stored in these registers are loaded into a shift register for placement in the appropriate bit
position in the outgoing data stream. The CPU can watch for the setting of the TLS1.TM
F latched status bit on
multiframe boundaries to know when to update any Tx signaling bits that may need to be changed.
Signaling data can be sourced from the TS registers on a per-channel basis by using the TSSIE registers.
In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1 - TS12 cont
ain a full
multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B), and
the C and D bit positions in the TS registers are ig
nored. In T1 mode, software signaling is enabled by setting
TCR1-T1.TS
SE=1. When software signaling is enabled, signaling bits are sourced from the TS registers for each
channel where the appropriate bit is set to 1 in the TSSIE registers.
In E1 mode, timeslot 16 carries the signaling information. This information can be in either CCS (Common Channel
Signaling) or CAS (Channel Associated Signaling) format. Only CAS is supported by the signaling logic described
in this section. In E1 mode the TCR1-E1.T16S bit
specifies how Tx signaling is sourced. When T16S=1, CAS
signaling bits for all timeslots is unconditionally sourced from the TS re
gisters. When T16S=0, signaling bits are
sourced from the TS regi
sters for each channel where the appropriate bit is set to 1 in the TSSIE registers. This
latter mode allows some signaling data for some channels to be sourced from the TS registe
rs while signaling data
for other channels can be sourced from the formatters TSIG input (hardware-based signaling).
Note that in E1 the 32 timeslots are referenced by two different channel number schemes in E1. In “channel”
numbering, TS0 through TS31 are labeled channels 1 through 32. In “phone channel” numbering, TS1 through
TS15 are labeled channels 1 through 15, and TS17 through TS31 are labeled channels 16 through channel 30.
This is illustrated below.
Table 10-41. Timeslot Number Schemes
TS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Channel
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Phone
Channel
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30