Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name Description Functions Page
TCR2-E1
Transmit Control Register 2 (E1 Mode) Tx enable for auto-E bit setting
289
TCR3
Transmit Control Register 3 Tx or D4 mode, CRC-4 recalc
290
TSLC
Transmit SLC96 Control Register 1,2,3 Tx SLC-96 Bits
280
TAF
Transmit Align Frame Tx possible source of Si, FAS bits
281
TNAF
Transmit Non-Align Frame Tx possible source of Si, A, Sa bits
281
RMMR
Receive Master Mode Register Rx E1/T1 mode, reset, initialization
244
RCR1-T1 Receive Control Register 1 (T1 Mode) Rx ESF or D4 mode, Japanese CRC-4
245
RCR1-E1
Receive Control Register 1 (E1 Mode) Rx CRC-4 enable/disable
246
RCR2-T1
Receive Control Register 2 (T1 Mode) Rx SLC-96 enable, LOF Criteria
229
RCR2-E1
Receive Control Register 2 (E1 Mode) Rx Loss of Signal Criteria Selection
247
RAF
E1 Receive Align Frame Register Received Si, FAS bits
238
RNAF
E1 Receive Non-Align Frame Register Received Si, A, Sa bits
239
RSLC
Receive SLC96 Control Register 1,2,3 Receive SLC-96 Bits
238
10.11.2 T1 Transmit Frame Synchronizer
The transmitter has the ability to identify the T1 SF or ESF frame boundary, as well as the E1 CRC-4 multiframe
boundary within the incoming data stream at TSER. The TCR3.TFM control
bit determines whether the transmit
synchronizer searches for the SF or ESF multiframe. Additional control signals for the transmit synchronizer are
located in the TSYNCC Re
gister. The latched status bit TLS3.LOFD indicates that a loss of frame synchronization
has occurred, and the real-time bit LOF is set high when the synchronizer is searching for frame/multiframe
alignment. The LOFD bit can be enabled to cause an interrupt request if enabled.
Note that when the transmit synchronizer is used, the TSYNC signal should be configured as an output
(TIOCR.TSIO
=1). When TIOCR.TSM=0, the recovered frame sync pulse is output on TSYNC. When
TIOCR.TSM=0, the recovered CRC-4 mu
ltiframe pulse is output on TSYNC.
Other key points concerning the transmit synchronizer:
1. The Tx synchronizer is not operational when the transmit elastic store is enabled.
2. The Tx synchronizer does not perform CRC-6 alignment verification (ESF mode) and does not
verify CRC-4 codewords.
3. The Tx synchronizer does not have the ability to search for the CAS multiframe.
The registers related to the transmit synchronizer are shown in the following table:
Table 10-39. Registers Related to the Transmit Synchronizer
Register Name Description Functions Page
TCR3
Transmit Control Register 3
TFM Bit Selects Between D4 and ESF 290
TIOCR
Transmit I/O Configuration Register TSYNC Should Be Set as an Output
291
TSYNCC
Transmit Synchronizer Control Register
Resynchronization Control for the 295
TLS3
Transmit Latched Status Register 3
Provides Latched Status for the 297
TIM3
Transmit Interrupt Mask Register 3
Provides Mask Bits for the TLS3 299
10.11.3 Signaling
The receive framer and transmit formatter support both software- and hardware-based signaling. Interrupts can be
generated on changes of signaling data. The framers are additionally equipped with a feature that freezes receive
signaling when any of these events occur: loss of signal, loss of frame, or change of frame alignment. The following
table lists register related to signaling.