Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
106 of 366
Interrupt Type Interrupt Procedure
CW_bits_change
1. Clear the CW_bits_change bit in the Intpend register by writing 1 to
it.
2. Read the CW_bits_change_low_bundles and
2CW_bits_change_high_bundles registers to determine which
bundles(s) have control bits that have changed.
3. Clear the set bits in the CW_bits_change_low_bundles an
d
2CW_bits_change_high_bundles registers by writing 1 to them.
4. Read the state of the control word fields from the Packet Classifier
Status regi
ster in the per-bundle status tables (section 11.4.4.1).
JB_underrun_Pn
1. Read the JBC_underrun bits in the Intpend register to determine
which port(s) are indicating jitter buffer underrun.
2. Clear the set JBC_underrun bits in the Intpend regi
ster by writing 1
to them.
3. Read the corresponding JBC_underrun regis
ter(s) to determine
which buffers had underruns.
4. Clear the set bits in the JBC_underrun registe
r(s) by writing 1 to
them.
5. Service the underrun(s) as needed.
ETH_MAC
1. Clear the ETH_MAC bit in the Intpend register by writing 1 to it.
2. Read the MAC_interrupt_status re
gister to determine the source(s)
of interrupts in the MAC (all bits are reset to 0 upon read).
3. Service the source(s) of the interrupt(s).
If a bit in the Intpend
register is set and that interrupt is then masked, the device generates an interrupt immediately
after the CPU clears the corresponding mask bit. To avoid this behavior, the CPU should clear the interrupt from
the Intpend registe
r before clearing the mask bit.
10.9.2 LIU, Framer and BERT Interrupts
Figure 10-64 is a flow diagram that shows how to deal with an interrupt on the H_INT[1] pin (or the H_INT[0] pin
when GCR1.I
POR=1). The CPU first reads the GTISR register to identify which LIU(s), Framer(s) or BERT(s) are
generating the interrupt request(s). For LIU interrupts, the CPU then reads the corresponding LLSR re
gister(s) to
identify the source of the interrupt(s). For BERT interrupts, the CPU reads the corresponding BSRL regi
ster(s).
For framer interrupts, the CPU reads the framer’s interrupt information registers (TIIR, RIIR) to fu
rther identify the
source of the interrupt(s). If TIIR indica
tes interrupt(s), the CPU then reads the corresponding transmit latched
status register(s) to determine the source(s) of the interrupts. If RIIR indicates in
terrupt(s), the CPU then reads the
corresponding receive latched status register(s) to determine the source(s) of the interrupts. The TIIR and
RIIR bits
are real-time bits that clear after the corresponding interrupt(s) have been cleared, as long as no additional, un-
masked interrupt conditions are present in the associated latched status registers.
All latched status bits in the LIUs, framers and BERTs are cleared by the CPU writing 1 to the bit. Latched status
bits that have been masked via interrupt mask registers do not affect the bits in the framer interrupt information
registers. The Interrupt mask bits prevent individual latched status conditions from generating interrupts, but they
do not prevent the latched status bits from being set. Therefore, when servicing interrupts, the CPU should
consider the interrupt mask bits in order to exclude latched status bits for which interrupts are masked. This
architecture allows the CPU to periodically poll the latched status bits for non-interrupt conditions, while using only
one set of registers.