Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
104 of 366
10.7 Global Resources
See the top-level block diagram in Figure 6-1. Global resources in the device include CLAD1, CLAD2, the CPU
Interface block, and the TDM Cross-Connection and External Interfaces block. These resources are configured in
the global registers described in section 11.3. The
se registers also handle device identification, top-level mode
configuration, I/O pin configuration, global resets, and top-level interrupts.
10.8 Per-Port Resources
See the top-level block diagram in Figure 6-1. Each port consists of the transmit and receive paths of an E1/T1/J1
LIU, an E1/T1/J1 framer, an HDLC controller, a BERT block, and one port of the TDM Cross-Connection and
External Interfaces block, and one port of the TDMoP block. These blocks are described in the following sections:
 LIUs: section 10.13
 Frame
rs: section 10.11
 HDLC:
section 10.12
 B
ERT: section 10.14
 TDMoP
: section 10.6
 Cro
ss-Connect: section 8
In addition, when u
sing the TDMoP block in external mode (see section 8.2) the port can b
e configured as a serial
data port that can connect to a serial interface transceiver for V.35 or RS-530 support. This would usually be in a
DCE application of some kind. The port can be configured for this mode by setting Port[n]_cfg_reg:Int_type=
00.
The device also features one 10/100 Ethernet port that can be configured to have an MII, RMII or SSMII interface.
The Ethernet port can work in half or full duplex mode and supports VLAN tagging and priority labeling according to
802.1p 802.1Q, including VLAN stacking. Section 11.4.16 de
scribes the Ethernet port.
10.9 Device Interrupts
H_INT[0] indicates interrupt requests from the TDMoP block. H_INT[1] indicates interrupt requests from the LIU,
framer and BERT. Optionally, the H_INT[1] si
gnal can be forced inactive at the pin and internally ORed into the
H_INT[
0] signal by setting GCR1.IPOR=1. This allows H_INT[0] to indicate interrupt requests from any and all
sources in the device. When GCR1.IPI0=
1, H_INT[0] is forced high (inactive). When GCR1.IPI1=1, H_INT[1] is
forced high (inactive). See Figure 10-63.
10.9.1 TDMoP Interrupts
The Intpend register indicates the source(s) of interrupt(s) from the TDMoP block. If one of the Intpend bits is set, it
can be cleared only by writing 1 to it. At reset, all Intpend interru
pts are disabled due to the Intmask register default
values. Writing 0 to an Intmask bit enabl
es the corresponding Intpend interrupt.