Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 94 of 198
11.4.1 Configuration and Status Registers
The base address for the TDMoP configuration and status registers is 0x0,000.
Table 11-4. TDMoP Configuration Registers
Addr
Offset
Register Name Description Page
0x00
General_cfg_reg0
General configuration register0
95
04
General_cfg_reg1
General configuration register1
96
08
General_cfg_reg2
General configuration register2
97
0C
Port1_cfg_reg
Port 1 configuration register
97
10
Port2_cfg_reg
Port 2 configuration register
97
14
Port3_cfg_reg
Port 3 configuration register
97
18
Port4_cfg_reg
Port 4 configuration register
97
1C
Port5_cfg_reg
Port 5 configuration register
97
20
Port6_cfg_reg
Port 6 configuration register
97
24
Port7_cfg_reg
Port 7 configuration register
97
28
Port8_cfg_reg
Port 8 configuration register
97
2C
Rst_reg
Reset register
100
30
TDM_cond_data_reg
TDM AAL1/SAToP conditioning data register
101
34
ETH_cond_data_reg
Ethernet AAL1/SAToP conditioning data register
101
38
Packet_classifier_cfg_reg0
Packet classifier configuration register0
101
3C
Packet_classifier_cfg_reg1
Packet classifier configuration register1
101
40
Packet_classifier_cfg_reg2
Packet classifier configuration register2
101
44
Packet_classifier_cfg_reg3
Packet classifier configuration register3
102
48
Packet_classifier_cfg_reg4
Packet classifier configuration register4
103
4C
Packet_classifier_cfg_reg5
Packet classifier configuration register5
103
50
Packet_classifier_cfg_reg6
Packet classifier configuration register6
103
54
Packet_classifier_cfg_reg7
Packet classifier configuration register7
103
58
Packet_classifier_cfg_reg8
Packet classifier configuration register8
104
5C
Packet_classifier_cfg_reg9
Packet classifier configuration register9
104
60
Packet_classifier_cfg_reg10
Packet classifier configuration register10
104
64
Packet_classifier_cfg_reg11
Packet classifier configuration register11
104
68
Packet_classifier_cfg_reg12
Packet classifier configuration register12
104
6C
Packet_classifier_cfg_reg13
Packet classifier configuration register13
105
70
Packet_classifier_cfg_reg14
Packet classifier configuration register14
105
74
Packet_classifier_cfg_reg15
Packet classifier configuration register15
105
78
Packet_classifier_cfg_reg16
Packet classifier configuration register16
105
7C
Packet_classifier_cfg_reg17
Packet classifier configuration register17
105
80
Packet_classifier_cfg_reg18
Packet classifier configuration register18
105
D4
CPU_rx_arb_max_fifo_level_reg
Rx arbiter maximum FIFO level register
106
Table 11-5. TDMoP Status Registers
Addr
Offset
Register Name Description Page
0xE0
General_stat_reg
General latched status register
107
E4
Version_reg
TDMoP version register
107
E8
Port1_sticky_reg1
Port 1 latched status register
107
EC
Port1_sticky_reg2
Port 2 latched status register
107
F0
Port1_sticky_reg3
Port 3 latched status register
107
F4
Port1_sticky_reg4
Port 4 latched status register
107
F8
Port1_sticky_reg5
Port 5 latched status register
107
FC
Port1_sticky_reg6
Port 6 latched status register
107
100
Port1_sticky_reg7
Port 7 latched status register
107
104
Port1_sticky_reg8
Port 8 latched status register
107
108
Port1_status_reg1
Port 1 status bit register 1
108
10C
Port1_status_reg2
Port 1 status bit register 2
108