Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 91 of 198
11.3 Global Registers
Functions contained in the global registers include device ID, CLAD configuration and top-level interrupt masking.
The global register base address is 0x108,000.
Table 11-2. Global Registers
Addr
Offset
Register Name R/W Description Page
0x00
GCR1
R/W
Global Control Register 1
91
08
GTRR
R/W
Global Transceiver Reset Register
91
0C
IDR
RO
Identification Device Register
92
10
GTISR
RO
Global Transceiver Interrupt Status Register
92
14
GTIMR
R/W
Global Transceiver Interrupt Mask Register
92
GCR1 (Global Control Register) 0x00
Bits
Data Element Name
R/W
Default
Description
[31:15]
Not Used
-
0
Must be set to zero.
[14]
SYSCLKS
R/W
0
TDMoP System Clock Frequency Select
When a 25MHz clock is applied to the CLK_SYS pin (i.e. when
the CLK_SYS_S pin is high), this bit configures the CLAD2 block
to provide either a 50MHz clock or a 75MHz clock to the TDMoP
block. When CLK_SYS_S=0 this bit is a don’t care. See section
10.4.
0 = 50MHz
1 = 75MHz
[13:12]
FREQSEL
R/W
00
Frequency Select
Specifies the frequency of the signal applied to the CLK_HIGH
pin.
00 = 38.88MHz (CLAD bypass; 38.88MHz in and out).
01 = 19.44MHz
10 = 10.000MHz
11 = 77.76MHz
[11:9]
Not Used
-
0
Must be set to zero.
[8]
CLK_HIGHD
R/W
0
CLK_HIGH Disable
Disables the 38.88MHz master clock to the clock recovery
machines of the TDMoP block to save power. This bit should be
set only when not using any of the TDMn_ACLK signals. See
section 10.4.
0 = Enabled
1 = Disabled
[7:0]
Not Used
-
0
Must be set to zero.
GTRR (Global Transceiver Reset Register) 0x08
Bits Data Element Name R/W Default Description
[31:19]
Not Used
-
0
Must be set to zero.
[18]
TOPRST
R/W
0
TDMoP Core Software Reset
When set, this bit resets all of the TDMoP configuration registers
to their default value.
0 = Normal operation
1 = Reset the TDMoP core
[17:0]
Not Used
-
0
Must be set to zero.