Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 88 of 198
Interrupt Type
Interrupt Procedure
them.
5. Read the corresponding Rx CAS information from the Rx Line CAS
registers (section 11.4.10).
Tx_CAS_change
1. Read the Tx_CAS_change bits in the Intpend register to determine
which port(s) are indicating Tx CAS change.
2. Clear the set Tx_CAS_change bits in the Intpend register by writing
1 to them.
3. Read the corresponding Tx_CAS_change register(s) to determine
which timeslot(s) have been changed.
4. Clear the set bits in the Tx_CAS_change register(s) by writing 1 to
them.
5. Read the appropriate Tx CAS information from neighboring framer
IC(s).
CW_bits_change
1. Clear the CW_bits_change bit in the Intpend register by writing 1 to
it.
2. Read the CW_bits_change_low_bundles and
CW_bits_change_high_bundles registers to determine which
bundles(s) have control bits that have changed.
3. Clear the set bits in the CW_bits_change_low_bundles and
CW_bits_change_high_bundles registers by writing 1 to them.
4. Read the state of the control word fields from the
Packet Classifier
Status register in the per-bundle status tables (section 11.4.4.1).
JB_underrun_Pn
1. Read the JBC_underrun bits in the Intpend register to determine
which port(s) are indicating jitter buffer underrun.
2. Clear the set JBC_underrun bits in the Intpend register by writing 1
to them.
3. Read the corresponding JBC_underrun register(s) to determine
which buffers had underruns.
4. Clear the set bits in the JBC_underrun register(s) by writing 1 to
them.
5. Service the underrun(s) as needed.
ETH_MAC
1. Clear the ETH_MAC bit in the Intpend register by writing 1 to it.
2. Read the MAC_interrupt_status register to determine the source(s)
of interrupts in the MAC (all bits are reset to 0 upon read).
3. Service the source(s) of the interrupt(s).
If a bit in the Intpend register is set and that interrupt is then masked, the device generates an interrupt immediately
after the CPU clears the corresponding mask bit. To avoid this behavior, the CPU should clear the interrupt from
the Intpend register before clearing the mask bit.