Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 87 of 198
10.7 Global Resources
See the top-level block diagram in Figure 6-1. Global resources in the device include CLAD1, CLAD2 and the CPU
Interface block. These resources are configured in the global registers described in section 11.3. These registers
also handle device identification, top-level mode configuration, I/O pin configuration, global resets, and top-level
interrupts.
10.8 Per-Port Resources
See the top-level block diagram in Figure 6-1. Each port is independently configured in the Port[n]_cfg_reg register.
In addition to E1 and T1 modes, a port can also be configured as a serial data port that can connect to a serial
interface transceiver for V.35 or RS-530 support. This would usually be in a DCE application of some kind. The
port can be configured for this mode by setting Port[n]_cfg_reg:Int_type=00.
The device also features one 10/100 Ethernet port that can be configured to have an MII, RMII or SSMII interface.
The Ethernet port can work in half or full duplex mode and supports VLAN tagging and priority labeling according to
802.1p 802.1Q, including VLAN stacking. Section 11.4.16 describes the Ethernet port.
10.9 Device Interrupts
The H_INT pin indicates interrupt requests. The only source for interrupts in the DS34S10x devices is the TDMoP
block (which includes the MAC). The TDMoPIM bit in GTIMR must be set to 1 enable interrupts from the TDMoP
block. The Intpend register indicates the source(s) of interrupt(s) from the TDMoP block. If one of the Intpend bits is
set, it can be cleared only by writing 1 to it. At reset, all Intpend interrupts are disabled due to the Intmask register
default values. Writing 0 to an Intmask bit enables the corresponding Intpend interrupt.
The TDMoP interrupts indicated in the Intpend register are of two types. The first type consists of interrupts
generated by a single source. The second type consists of interrupts that can originate from any of several possible
interrupt sources including the ETH_MAC, CW_bits_change, Rx_CAS_change, Tx_CAS_Change, and
JB_underrun interrupts.
The JBC_underrun interrupts can be masked per timeslot by setting the appropriate bits in the
JBC_underrun_mask registers.
The Tx_CAS_change interrupts can be masked per timeslot by setting the appropriate bits in the
Tx_CAS_change_mask registers.
The CW_bits_change interrupts can be masked per bundle by setting the appropriate bits in the CW_bits_mask
registers. In addition, the fields of the control word that cause an interrupt when changed (L, R, M, FRG) can be
configured in the CW_bits_change_mask register.
When an interrupt is indicated on H_INT, the CPU should read the Intpend register to identify the interrupt source
and then proceed as follows:
Interrupt Type
Interrupt Procedure
Single-source Interrupts
1. Clear the pending interrupt(s) by writing 1 to the corresponding
Intpend bit(s).
2. Service the source of the interrupt.
Rx_CAS_change
1. Read the Rx_CAS_change bits in the Intpend register to determine
which port(s) are indicating Rx CAS change.
2. Clear the set Rx_CAS_change bits in the Intpend register by writing
1 to them.
3. Read the corresponding Rx_CAS_change register(s) to determine
which timeslot(s) have been changed.
4. Clear the set bits in the Rx_CAS_change register(s) by writing 1 to