Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 78 of 198
10.6.11.14 Ethernet to CPU Flow
Ethernet packets enter the chip via the Ethernet MAC block and the packet classifier into the Rx arbiter. When the
Rx arbiter identifies that a packet is destined to the CPU, it extracts a pointer from the Ethernet-to-CPU pool (if the
pool is empty, the Rx arbiter discards the packet) and stores the packet data into the SDRAM in the buffer
indicated by the pointer. Then, it sends the pointer to the Ethernet-to-CPU queue (processed by the CPU). If the
queue is full, the Rx arbiter keeps the pointer for itself for future use. The Ethernet-to-CPU queue and pool contain
up to 128 pointers each. Section 11.4.6 describes the pool and queue registers.
Figure 10-57. Ethernet-to-CPU Flow
10.6.12 Ethernet MAC
10.6.12.1 Introduction
The Ethernet MAC can operate at 10 or 100 Mbps. It supports MII, RMII (Reduced pin-count MII), and SSMII
(source-synchronous serial MII). The MAC interface to the physical layer must be configured by the CPU.
The UNH-tested Ethernet MAC complies with IEEE 802.3. Its counters enable the software to generate network
management statistics compatible with IEEE 802.3 Clause 5.
The Ethernet MAC supports physical layer management through an MDIO interface. The control registers drive the
MDIO interface and select modes of operation, such as full or half duplex. Half-duplex flow control is achieved by
forcing collisions on incoming packets. Full-duplex flow control supports recognition of incoming pause packets.
In the receive path, the MAC checks the incoming packets for valid preamble, FCS, alignment and length, and
presents received packets to the packet classifier. Although packets with physical errors are discarded by default,
the MAC can be configured to ignore errors and keep such packets.
In the transmit path, the MAC takes data from the Tx Ethernet interface, adds preamble and, if necessary, pad and
FCS, then transmits data according to the CSMA/CD (carrier sense multiple access with collision detect) protocol.
PACKET
CLASSIFIER
SDRAM
RX ARBITER
ETH TO
CPU
POOL
ETH TO
CPU
QUEUE
LOOP CLOSED BY CPU
ETH MAC
TDMoP Block