Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 63 of 198
Figure 10-45. SDRAM Access through the SDRAM Controller
CPU
SDRAM
TDMoPacket
SDRAM CONTROLLER
CONFIGURATION
REGISTER
RESET_N
CONFIGURATION
BITS
ACCESS FROM
HW BLOCKS
CPU PORTOTHER PORTS
ARBITER
CLOCK
10.6.10 Jitter Buffer Control (JBC)
10.6.10.1 Jitter Buffer Application
Routinely in TDM networks, destination TDM devices derive a clock from the incoming TDM signal and use it for
transmitting data as depicted in Figure 10-46. This is called loopback timing.
Figure 10-46. Loop Timing in TDM Networks
SOURCE TDM
DEVICE
DESTINATION
TDM DEVICE
LOOPBACK
TIMING
SOURCE
CLOCK
When replacing the physical TDM connection with an IP/MPLS network and two TDM-over-Packet devices as
shown in Figure 10-47 below, the receiving TDM-over-Packet device (slave) receives packets with variable delays
(packet delay variation). After processing, the slave TDMoP device should send TDM data to the destination TDM
device at the same clock rate at which the TDM data was originally sent by the source TDM device. To achieve
this, the device works in clock recovery mode to reconstruct the source TDM clock to allow the destination TDM
device to still work in loopback timing mode.