Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 6 of 198
List of Tables
Table 3-1. Applicable Standards ......................................................................................................................... 10
Table 9-1. Short Pin Descriptions ........................................................................................................................ 18
Table 9-2. TDM-over-Packet Engine TDM Interface Pins..................................................................................... 20
Table 9-3. SDRAM Interface Pins........................................................................................................................ 22
Table 9-4. Ethernet PHY Interface Pins (MII/RMII/SSMII) .................................................................................... 23
Table 9-5. Global Clock Pins ............................................................................................................................... 24
Table 9-6. CPU Interface Pins ............................................................................................................................. 25
Table 9-7. JTAG Interface Pins ........................................................................................................................... 27
Table 9-8. Reset and Factory Test Pins .............................................................................................................. 27
Table 9-9. Power and Ground Pins ..................................................................................................................... 27
Table 10-1. CPU Data Bus Widths ...................................................................................................................... 29
Table 10-2. SPI Write Command Sequence ........................................................................................................ 34
Table 10-3. SPI_ Read Command Sequence ...................................................................................................... 35
Table 10-4. SPI Status Command Sequence ...................................................................................................... 36
Table 10-5. Reset Functions ............................................................................................................................... 37
Table 10-6. Ethernet Packet Fields ..................................................................................................................... 38
Table 10-7. IPv4 Header Fields (UDP) ................................................................................................................ 40
Table 10-8. UDP Header Fields .......................................................................................................................... 40
Table 10-9. IPv6 Header Fields (UDP) ................................................................................................................ 41
Table 10-10. MPLS Header Fields ...................................................................................................................... 41
Table 10-11. MEF Header Fields ........................................................................................................................ 41
Table 10-12. IPv4 Header Fields (L2TPv3) .......................................................................................................... 42
Table 10-13. L2TPv3 Header Fields .................................................................................................................... 42
Table 10-14. IPv6 Header Fields (L2TPv3) .......................................................................................................... 43
Table 10-15. Control Word Fields ........................................................................................................................ 43
Table 10-16. RTP Header Fields ......................................................................................................................... 44
Table 10-17. VCCV OAM Payload Fields ............................................................................................................ 45
Table 10-18. UDP/IP-Specific OAM Payload Fields ............................................................................................. 46
Table 10-19. CAS – Supported Interface Connections for AAL1 and CESoPSN .................................................. 51
Table 10-20. CAS Handler Selector Decision Logic ............................................................................................. 52
Table 10-21. AAL1 Header Fields ....................................................................................................................... 55
Table 10-22. SDRAM Access Resolution ............................................................................................................ 62
Table 10-23. SDRAM CAS Latency vs. Frequency .............................................................................................. 62
Table 10-24. Buffer Descriptor First Dword Fields (Used for all Paths) ................................................................. 68
Table 10-25. Buffer Descriptor Second Dword Fields (TDM  ETH and CPU  ETH) ........................................ 69
Table 10-26. Buffer Descriptor Second Dword Fields (ETH  CPU) ................................................................... 69
Table 10-27. Buffer Descriptor Third Dword Fields (ETH  CPU) ....................................................................... 70
Table 10-29. Start of an 802.3 Pause Packet ...................................................................................................... 80
Table 10-30. Handling IPv4 and IPv6 Packets ..................................................................................................... 81
Table 10-31. TDMoIP Port Number Comparison for TDMoIP Packet Classification .............................................. 83
Table 10-32. Bundle Identifier Location and Width ............................................................................................... 83
Table 11-1. Top-Level Memory Map .................................................................................................................... 90
Table 11-2. Global Registers ............................................................................................................................... 91
Table 11-3. TDMoP Memory Map ....................................................................................................................... 93
Table 11-4. TDMoP Configuration Registers ....................................................................................................... 94
Table 11-5. TDMoP Status Registers .................................................................................................................. 94
Table 11-6. Counters Types .............................................................................................................................. 117
Table 11-7. CPU Queues .................................................................................................................................. 124
Table 11-8. Jitter Buffer Status Tables .............................................................................................................. 130
Table 11-9. Bundle Timeslot Tables .................................................................................................................. 130
Table 11-10. Transmit Software CAS Registers ................................................................................................ 134
Table 11-11. Receive Line CAS Registers......................................................................................................... 136
Table 11-12. Clock Recovery Registers ............................................................................................................ 137
Table 11-13. Receive SW Conditioning Octet Select Registers ......................................................................... 138
Table 11-14. Receive SW CAS Registers.......................................................................................................... 139