Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 5 of 198
Figure 10-53. TDM-to-TDM Flow ......................................................................................................................... 74
Figure 10-54. TDM-to-CPU Flow ......................................................................................................................... 75
Figure 10-55. CPU-to-TDM Flow ......................................................................................................................... 76
Figure 10-56. CPU-to-Ethernet Flow ................................................................................................................... 77
Figure 10-57. Ethernet-to-CPU Flow ................................................................................................................... 78
Figure 10-59. Ethernet MAC ............................................................................................................................... 79
Figure 10-60. Format of TDMoIP Packet with VLAN Tag ..................................................................................... 82
Figure 10-61. Format of TDMoMPLS Packet with VLAN Tag ............................................................................... 82
Figure 10-62. Format of TDMoMEF Packet with VLAN Tag ................................................................................. 82
Figure 10-63. Structure of Packets with Trailer .................................................................................................... 85
Figure 11-1. 16-Bit Addressing ............................................................................................................................ 89
Figure 11-2. 32-Bit Addressing ............................................................................................................................ 89
Figure 11-3. Partial Data Elements (shorter than 16 bits)..................................................................................... 89
Figure 11-4. Partial Data Elements (16 to 32 bits long) ........................................................................................ 90
Figure 12-1. JTAG Block Diagram ..................................................................................................................... 158
Figure 12-2. JTAG TAP Controller State Machine ............................................................................................. 159
Figure 14-1. RST_SYS_N Timing...................................................................................................................... 164
Figure 14-2. CPU Interface Write Cycle Timing ................................................................................................. 165
Figure 14-3. CPU Interface Read Cycle Timing ................................................................................................. 165
Figure 14-4. SPI interface Timing (SPI_CP = 0) ................................................................................................ 166
Figure 14-5. SPI interface Timing (SPI_CP = 1) ................................................................................................ 166
Figure 14-6. SDRAM Interface Write Cycle Timing ............................................................................................ 167
Figure 14-7. SDRAM Interface Read Cycle Timing ............................................................................................ 168
Figure 14-8. TDMoP TDM Timing, One-Clock Mode (Two_clocks=0, Tx_sample=1) ......................................... 169
Figure 14-9. TDMoP TDM Timing, One Clock Mode (Two_clocks=0, Tx_sample=0) ......................................... 170
Figure 14-10. TDMoP TDM Timing, Two Clock Mode (Two_clocks=1, Tx_sample=1, Rx_sample=1) ................ 170
Figure 14-11. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=0) ............... 170
Figure 14-12. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=1) ............... 171
Figure 14-13. TDMoP TDM Timing,Two Clocks Mode (Two_clocks=1, Tx_sample=1, Rx_sample=0)................ 171
Figure 14-14. MII Management Interface Timing ............................................................................................... 172
Figure 14-15. MII Interface Output Signal Timing............................................................................................... 172
Figure 14-16. MII Interface Input Signal Timing ................................................................................................. 173
Figure 14-17. RMII Interface Output Signal Timing ............................................................................................ 173
Figure 14-18. RMII Interface Input Signal Timing ............................................................................................... 173
Figure 14-19. SSMII Interface Output Signal Timing .......................................................................................... 174
Figure 14-20. SSMII Interface Input Signal Timing ............................................................................................. 174
Figure 14-21. JTAG Interface Timing Diagram .................................................................................................. 175
Figure 15-1. Connecting Port 1 to a Serial Transceiver ...................................................................................... 176
Figure 15-2. Connecting the Ethernet Port to a PHY in MII Mode ...................................................................... 177
Figure 15-3. Connecting the Ethernet Port to a MAC in MII Mode ...................................................................... 177
Figure 15-4. Connecting the Ethernet Port to a PHY in RMII Mode .................................................................... 177
Figure 15-5. Connecting the Ethernet Port to a MAC in RMII Mode ................................................................... 178
Figure 15-6. Connecting the Ethernet Port to a PHY in SSMII Mode .................................................................. 178
Figure 15-7. Connecting the Ethernet Port to a MAC in SSMII Mode ................................................................. 178
Figure 15-8. External Clock Multiplier for High Speed Applications .................................................................... 179
Figure 15-9. 32-Bit CPU Bus Connections......................................................................................................... 180
Figure 15-10. 16-Bit CPU Bus Connections ....................................................................................................... 181
Figure 15-11. Connecting the H_READY_N Signal to the MPC860 TA Pin ....................................................... 182
Figure 15-12. Internal CPLD Logic to Synchronize H_READY_N to the MPC860 Clock ..................................... 182
Figure 16-1. DS34S101 Pin Assignment (TE-CSBGA Package) ........................................................................ 190
Figure 16-2. DS34S102 Pin Assignment (TE-CSBGA Package) ........................................................................ 191
Figure 16-3. DS34S104 Pin Assignment (TE-CSBGA Package) ........................................................................ 192
Figure 16-4. DS34S108 Pin Assignment (HSBGA Package) ............................................................................. 196