Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 49 of 198
of the CLK_HIGH signal depend on the wander requirements of the recovered TDM clock. For applications where
the recovered TDM clock must comply with G.823/G.824 requirements for traffic interfaces, typically a TCXO can
be use as the source for the CLK_HIGH signal. For applications where the recovered clock must comply with
G.823/G.824 requirements for synchronization interfaces, the CLK_HIGH signal typically must come from an
OCXO.
In addition to performing clock recovery for up to eight low-speed (typically E1/T1) signals, the device can also be
configured in a high-speed mode in which it supports one E3, T3 or STS-1 signal in and out of port 1. In high-speed
mode, the on-chip digital PLL synthesizes the recovered clock frequency divided by 10 (for STS-1) or 12 (for E3 or
T3). This clock is available on the TDM1_ACLK output pin and can be multiplied by an external PLL to get the
recovered clock of the high-speed signal (see section 15.3). High-speed mode is enabled when High_speed=1 in
General_cfg_reg0.
For applications where the chip is used only for clock recovery purposes (i.e. data is not forwarded through the
chip) the external SDRAM is not needed.
10.6.4 Timeslot Assigner (TSA)
The TDM-over-Packet block contains one Timeslot Assigner for each TDM port (framed or multiframed). The TSA
is bypassed in high-speed mode (i.e. when High_speed=1 in General_cfg_reg0.) The TSA tables are described in
section 11.4.5.
The TSA assigns 2-, 7- or 8-bit wide timeslots to a specific bundle and a specific receive queue. 2-bit timeslots are
used for delivering 16K HDLC channels. The 2 bits are located at the first 2 bits (PCM MSbits, HDLC LSbits) of the
timeslot. The next 6 bits of the timeslot cannot be assigned. 7-bit timeslots are used for delivering 56kbps HDLC
channels. The 7 bits are located at the first 7 bits (PCM MSbits, HDLC LSbits) of the timeslot. The last bit of the
timeslot cannot be assigned. The 2-bit and 7-bit timeslots may be assigned only to the HDLC payload type
machine. The AAL1 and RAW payload type machines support only 8-bit timeslots. For unframed/Nx64 interfaces
all entries must be configured as 8-bit timeslots.
Each port has two TSA tables (banks): one active and the other one shadow. The TSA_int_act_blk status bit in
Port[n]_stat_reg1 indicates which bank is currently active. The CPU can only write to the shadow table. After TSA
entries are changed in the shadow table the TSA tables should be swapped by changing the TSA_act_blk bit in
Port[n]_cfg_reg so that the active table becomes the shadow table and the shadow table becomes the active table.
Changes take effect at the next frame sync signal. For an unframed interface the changes take effect up to 256
TDM clock cycles after the TSA_act_blk is changed. After the change occurs, the TSA_int_act_blk bit is updated by
the device.
Each table consists of 32 entries, one entry per timeslot. The first entry refers to the first timeslot, i.e. the first 8 bits
of the frame (where the frame sync signal indicates start-of-frame). The second entry refers to the second timeslot,
i.e. the 8 bits after the first 8 bits, and so on.
The format of a table entry is shown in section 11.4.5. If a port is configured for an unframed signal format, all 32
entries for that port must have the same settings for all fields.
A bundle can only be composed of timeslots from a single TDM port, but timeslots from a TDM port can be
assigned to multiple bundles.