Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 48 of 198
Figure 10-25. TDMoMPLS Packet Format in a Typical Application
1
2
DA
SA
VLAN Tag
Optional
Ethertype
MPLS
Outer MPLS
Label(s)
Optional
Inner MPLS
Label
Bundle ID=A
Control
Word
Payload Type
AAL1/
HDLC/SAToP/
CESoPSN/OAM
CRC-32
3
4
DA
SA
VLAN Tag
Optional
Ethertype
MPLS
Outer MPLS
Label(s)
Optional
Inner MPLS
Label
Bundle ID=B
Control
Word
Payload Type
AAL1/
HDLC/SAToP/
CESoPSN/OAM
CRC-32
10.6.3 Clock Recovery
The TDM-over-Packet block’s innovative clock recovery process is divided into two successive phases. In the
acquisition phase, rapid frequency lock is attained. In the tracking phase, frequency lock is sustained and phase is
also tracked. During the tracking phase, jitter is attenuated to comply with the relevant telecom standards even for
packet-switched networks with relatively large packet delay variation. Packet loss immunity is also significantly
improved.
During the acquisition phase, a direct estimation of the frequency discrepancy between the far-end and near-end
service clocks continuously drives an internal frequency synthesis device through a band-limited control loop. As a
result, frequency acquisition is achieved rapidly (typically less than 10 seconds). The clock recovery capture range
is ±90 ppm around the nominal service clock for any supported clock rate.
Once the frequency-monitoring unit has detected a steady frequency lock, the system switches to its tracking
phase. During the tracking phase the fill level of the received-packet jitter buffer drives the internal frequency
synthesizer through a similar band-limited control loop.
While in the tracking phase, two tasks are performed. First, the far-end service clock frequency is slowly and
accurately tracked, while compelling the regenerated near-end service clock to have jitter and wander levels that
conform to ITU-T G.823/G.824 requirements, even for networks that introduce high packet delay variation and
packet loss. This performance can be attained due to a very efficient jitter attenuation mechanism, combined with a
high resolution internal digital PLL (∆ƒ=0.4 ppb). Second, the received-packet jitter buffer is maintained at its fill
level, regardless of the initial frequency discrepancy between the clocks. As a result, the latency added by the
mechanism is minimized, while immunity against overflow/underflow events (caused by extreme packet delay
variation events) is substantially enhanced.
The TDM-over-Packet block supports two clock recovery modes: common clock (differential) mode and adaptive
mode.
The common clock mode is used for applications where the TDMoP gateways at both ends of the PSN path have
access to the same high-quality reference clock. This mode makes use of RTP differential mode time-stamps and
therefore the RTP header must be present in TDMoP packets when this mode is used. The common reference
clock is provided to the chip on the CLK_CMN input pin. The device is configured for common clock mode when
Clock_recovery_en=1 in General_cfg_reg0 and RTP_timestamp_generation_mode=1 in General_cfg_reg1.
The adaptive clock mode is based solely on packet inter-arrival time and therefore can be used for applications
where a common reference clock is not available to both TDMoP gateways. This mode does not make use of time-
stamps and therefore the RTP header is not needed in the TDMoP packets when this mode is used. The device is
configured for adaptive clock mode when Clock_recovery_en=1 in General_cfg_reg0 and
RTP_timestamp_generation_mode=0 in General_cfg_reg1.
In adaptive mode, for low-speed interfaces (up to 4.6 MHz), an on-chip digital PLL, clocked by a 38.88MHz clock
derived from the CLK_HIGH pin, synthesizes the recovered clock frequency. The frequency stability characteristics