Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 37 of 198
The TDM-over-packet block also requires a 50 MHz or 75 MHz clock (±50 ppm or better) to clock its internal
circuitry and the SDRAM interface (SD_CLK). When the CLK_SYS_S pin is low, a 50 MHz or 75 MHz clock applied
to the CLK_SYS pin is passed directly to the TDMoP block. When the CLK_SYS_S pin is high, a 25 MHz clock on
the CLK_SYS pin is internally multiplied by an analog PLL in the CLAD2 block to either 50 MHz or 75 MHz as
specified by GCR1.SYSCLKS.
10.5 Reset and Power-Down
A hardware reset is issued by forcing the RST_SYS_N pin low. This pin resets the TDM-over-Packet block and the
MAC. Note that not all registers are cleared to 0x00 on a reset condition. The register space must be reinitialized to
appropriate values after hardware or software reset has occurred. This includes setting reserved locations to 0.
Several block-specific resets are also available, as shown in Table 10-5.
Table 10-5. Reset Functions
RESET FUNCTION LOCATION COMMENTS
Hardware Device Reset RST_SYS_N Pin
Transition to a 200us or more logic 0 level resets the
device. CLK_SYS and CLK_HIGH/MCLK are
recommended to be stable 200us before transitioning
out of reset.
Hardware JTAG Reset JTRST_N Pin Resets the JTAG test port.
Resets TDMoP TX, RX paths Rst_reg
Used to reset the transmit (TX) and receive (RX) paths
of the TDM-over-Packet block.
Resets the SDRAM controller General_cfg_reg0 The Rst_SDRAM_n bit resets the SDRAM controller.
10.6 TDM-over-Packet Block
10.6.1 Packet Formats
To transport TDM data through packet switched networks, the TDM-over-Packet block encapsulates the TDM data
into Ethernet packets as depicted in Figure 10-10.