Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 33 of 198
10.3.3 SPI Signals
In SPI mode, the following CPU bus pins change their functionality and operate as SPI signals.
• Inputs
o SPI_CLK is shared with H_WR_BE0_N
o SPI_MOSI is shared with H_WR_BE1_N
o SPI_SEL_N is shared with H_WR_BE2_N.
• Outputs
o SPI_MISO is shared with H_D[0].
The SPI configuration is supplied on two external pins as follows:
• SPI_CI (clock invert) is shared with H_WR_BE3_N
• SPI_CP (clock phase) is shared with H_R_W_N.
In the SPI mode the device operates internally in 32-bit mode.
10.3.4 SPI Protocol
The external CPU communicates with the device over SPI by issuing commands. There are three command types:
1. Write – performs 32-bit write access
2. Read – performs 32-bit read access
3. Status – verifies that previous access has been finished
The SPI_SEL_N signal must be de-asserted between accesses to the device.
10.3.4.1 Write Command
The SPI write command proceeds as follows:
• The SPI master (CPU) starts a write access by asserting SPI_SEL_N (low).
• Then, during each SPI_CLK cycle a SPI_MOSI data bit is transmitted by the master (CPU), while a
SPI_MISO bit is transmitted by the slave (the device).
• The first bit on SPI_MOSI and SPI_MISO is reserved (don’t care).
• The master then transmits two opcode bits on SPI_MOSI. These bits specify a read, write or status
command. The value 01b represents a write command. At the same time, the slave transmits the opcode
bits of the previous command on SPI_MISO.
• The next four bits the master transmits on SPI_MOSI are byte-enable values: byte_en_3, byte_en_2,
byte_en_1, and byte_en_0 which are equivalent to the function of the H_WR_BE3_N to H_WR_BE0_N