Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 32 of 198
• SPI_MISO is master data input, slave data output.
• SPI_SEL_N is the slave chip select.
The master initiates a data transfer by asserting SPI_SEL_N (low) and generating a sequence of SPI_CLK cycles
accompanied by serial data on SPI_MOSI. During read cycles the slave outputs data on SPI_MISO. Each
additional slave requires an additional slave chip-select wire. Figure 10-7 illustrates a typical connection between
an SPI master and a single SPI slave.
Figure 10-7. SPI Interface with One Slave
SPI
Master
SPI
Slave
SPI_CLK
SPI_SEL_N
SPI_MOSI
SPI_MISO
10.3.2 SPI Modes
Two configuration pins define the SPI mode of operation.
• The polarity of SPI_CLK is specified by the SPI_CI (clock invert) input pin.
• The SPI_CP (clock phase) input pin determines whether the first SPI_CLK transition is used to sample the
data on SPI_MISO/SPI_MOSI (which requires the first bit to be ready beforehand on these lines) or to
updated the data on the SPI_MISO/SPI_MOSI lines. See Figure 10-8 and Figure 10-9.
Figure 10-8. SPI Interface Timing, SPI_CP=0
SPI_SEL_N
SPI_CLK(CI=0)
SPI_CLK(CI=1)
SPI_MOSI(input)
SPI_MISO(output)
msb
lsb
msb
lsb
Figure 10-9. SPI Interface Timing, SPI_CP=1
SPI_SEL_N
SPI_CLK(CI=0)
SPI_CLK(CI=1)
SPI_MOSI(input)
SPI_MISO(output)
msb lsb
msb lsb