Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 27 of 198
Table 9-7. JTAG Interface Pins
See the JTAG interface timing diagram in Figure 14-21.
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
JTRST_N
Ipu
JTAG Test Reset (Active Low)
This signal is used to asynchronously reset the test access port controller. After
power up, JTRST_N must be toggled from low to high. This action sets the device
into the JTAG DEVICE ID mode. Pulling JTRST_N low restores normal device
operation. If boundary scan is not used, this pin should be held low.
JTCLK
I
JTAG Test Clock
This signal is used to shift data into JTDI on the rising edge and out of JTDO on
the falling edge.
JTMS
Ipu
JTAG Test Mode Select
This pin is sampled on the rising edge of JTCLK and is used to place the test
access port into the various defined IEEE 1149.1 states. If not used, JTMS should
be held high.
JTDI
Ipu
JTAG Test Data Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. If
not used, JTDI can be held low or high (DVDDIO).
JTDO
Oz
8mA
JTAG Test Data Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK.
If not used, this pin should be left unconnected.
Table 9-8. Reset and Factory Test Pins
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
RST_SYS_N
Ipu
System Reset (Active Low)
When this pin is held low the entire device is reset. This pin should be held low
(active) for at least 200 µs before going inactive. CLK_SYS and CLK_HIGH should
be stable for at least 200 µs before RST_SYS_N goes inactive. See section 10.5
for more information on system resets and block-level resets.
HIZ_N
I
High Impedance Enable (Active Low)
When this signal is low while JTRST_N is low, all of the digital output and bi-
directional pins are placed in the high impedance state. For normal operation this
signal is high. This is an asynchronous input.
SCEN
I
Used during factory test. This pin should be tied to DVSS.
STMD
I
Used during factory test. This pin should be tied to DVSS.
MBIST_EN
I
Used during factory test. This pin should be tied to DVSS.
MBIST_DONE
O
Used during factory test. This pin should be left floating.
MBIST_FAIL
O
Used during factory test. This pin should be left floating.
TEST_CLK
O
Used during factory test. This pin should be left floating.
TST_CLD
I
Used during factory test. This pin should be tied to DVSS.
Table 9-9. Power and Ground Pins
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
DVDDC
P
1.8V Core Voltage for TDM-over-Packet Digital Logic (17 pins)
DVDDIO
P
3.3V for I/O Pins (16 pins)
DVSS
P
Ground for TDM-over-Packet Logic and I/O Pins (31 pins)
ACVDD1
P
1.8V for CLAD Analog Circuits
ACVDD2
P
1.8V for CLAD Analog Circuits
ACVSS1
P
Ground for CLAD Analog Circuits
ACVSS2
P
Ground for CLAD Analog Circuits