Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 26 of 198
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
1 = input data is latched on the trailing edge of the SCLK pulse; output data is
updated on the leading edge
H_WR_BE0_N /
SPI_CLK
I
H_WR_BE0_N: Host Write Enable Byte 0 (Active Low)
In parallel interface mode during a write access this pin specifies whether or not
byte 0 (H_D[7:0]) should be written to the device. This pin is active in both 32-bit
and 16-bit modes.
0 = write byte 0
1 = don’t write byte 0
SPI_CLK: SPI Clock
In SPI interface mode this pin is the clock for the interface.
H_WR_BE1_N /
SPI_MOSI
I
H_WR_BE1_N: Host Write Enable Byte 1 (Active Low)
In parallel interface mode during a write access this pin specifies whether or not
byte 1 (H_D[15:8]) should be written to the device. This pin is active in both 32-bit
and 16-bit modes.
0 = write byte 1
1 = don’t write byte 1
SPI_MOSI: SPI Data Input (Master Out Slave In)
In SPI interface mode this pin is the data input pin for the interface.
H_WR_BE2_N /
SPI_SEL_N
I
H_WR_BE2_N: Host Write Enable Byte 2 (Active Low)
In 32-bit parallel interface mode during a write access this pin specifies whether or
not byte 2 (H_D[15:8]) should be written to the device. In 16-bit parallel interface
mode this pin is ignored and should be pulled high or low.
0 = write byte 2
1 = don’t write byte 2
SPI_SEL: SPI Chip Select (Active Low)
In SPI interface mode this pin must be asserted (low) to read or write internal
registers.
H_WR_BE3_N /
SPI_CI
I
H_WR_BE3_N: Host Write Enable Byte 3 (Active Low)
In 32-bit parallel interface mode during a write access this pin specifies whether or
not byte 3 (H_D[15:8]) should be written to the device. In 16-bit parallel interface
mode this pin is ignored and should be pulled high or low.
0 = write byte 3
1 = don’t write byte 3
SPI_CI: SPI Clock Invert
In SPI interface mode this pin specifies the polarity of the SPI_CLK pin. See the
timing diagrams in Figure 14-4 and Figure 14-5 for details.
0 = SPI_CLK is normally low and pulses high (leading edge is rising edge)
1 = SPI_CLK is normally high and pulses low (leading edge is falling edge)
H_READY_N
O
8mA
Host Ready Output (Active Low)
In parallel interface mode the device pulls this pin low during a read or write
access to signal that the device is ready for the access to be completed. The host
processor should not pull
H_CS_N high (inactive) to complete the access until the device
has pulled H_READY_N low.
This pin requires the use of an external pull-up resistor. The device actively drives
this pin high before allowing it to go high-impedance. See Figure 14-2.
H_INT
O
8mA
Host Interrupt Output (Active Low)
This pin indicates interrupt requests from the device. When GCR1.IPI=1, H_INT is
forced high (inactive). See section 10.9.