Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 25 of 198
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
19.44 MHz (2430*8 kHz).
For systems using GPS, 8.184 MHz (1023*8 kHz).
For systems connected by a single hop of 100 Mbit/s Ethernet where it is possible
to lock the physical layer clock, 25 MHz (3125*8 kHz).
For systems connected by a single hop of Gigabit Ethernet where it is possible to
lock to the physical layer clock, 10MHz (1250*8 kHz).
When a clock is not needed on this pin, pull it high or low. See section 10.4.
CLK_HIGH
I
Clock High Input
A 10, 19.44, 38.88 or 77.76MHz clock can be applied to this pin. From the
CLK_HIGH signal, an on-chip frequency converter block (called a cl
ock adapter or
CLAD, in this case CLAD1) produces the 38.88MHz reference clock required by
the clock recovery machines in the TDMoP block.
GCR1.FREQSEL specifies the frequency of the clock applied to CLK_HIGH.
When GCR1.CLK_HIGHD=1, the CLAD disables the 38.88MHz reference clock to
the clock recovery machines.
When clock recovery is not required (i.e. when none of the recovered clock outputs
TDMn_ACLK are used), CLK_HIGH can be held low.
The required quality of the CLK_HIGH signal is discussed in section 10.6.3.
Table 9-6. CPU Interface Pins
See the parallel interface timing diagrams in Figure 14-2 and Figure 14-3 and the SPI timing diagrams in Figure 14-4 and Figure 14-5.
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
H_CPU_SPI_N
Ipu
Host Bus Interface
0 = SPI serial interface
1 = Parallel interface
DAT_32_16_N
Ipu
Data Bus Width
0 = 16-bit
1 = 32-bit
In SPI bus mode this pin is ignored.
H_D[31:1]
IO
8mA
Host Data Bus
When the device is configured for a 32-bit parallel interface, H_D[31:0] are the
data I/O pins (HD[31] is the MSb). When the device is configured for a 16-bit
parallel interface, H_D[15:0] are the data I/O pins (HD[15] is the MSb) and
H_D[31:16] are ignored and should be pulled low or high. The DAT_32_16_N
pin
specifies bus width. In SPI bus mode these pins are ignored.
H_D[0] /
SPI_MISO
IO
8mA
H_D[0]: Host Data LSb
In parallel interface mode this pin is H_D[0], LSb of the data bus.
SPI_MISO: SPI Data Output (Master In Slave Out)
In SPI bus mode this pin is the SPI data output.
H_AD[24:1]
I
Host Address Bus
H_AD[24] is the MSb. When the host data bus is 32 bits (DAT_32_16_N=1),
H_AD[1] should be held low. In SPI bus mode these pins are ignored.
H_CS_N
I
Host Chip Select (Active Low)
In parallel interface mode this pin must be asserted (low) to read or write internal
registers. In SPI bus mode this pin is ignored.
H_R_W_N /
SPI_CP
I
H_R_W_N: Host Read/Write Control
In parallel interface mode this pin controls whether an access to internal registers
is a read or a write.
SPI_CP: SPI Clock Phase
In SPI interface mode this pin specifies SPI clock phase. See the timing diagrams
in Figure 14-4 and Figure 14-5 for details.
0 = input data is latched on the leading edge of the SCLK pulse; output data is
updated on the trailing edge