Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 24 of 198
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
MII_RXD[3:0]
I
MII Receive Data Inputs
In MII mode, receive data comes from the PHY four bits at a time on MII_RXD[3:0],
on the rising edge of CLK_MII_RX. See the timing diagram in Figure 14-16.
In RMII mode, receive data comes from the PHY two bits at a time on
MII_RXD[3:2] and is latched on the rising edge of CLK_MII_TX. MII_RXD[1:0] are
not used. See the timing diagram in Figure 14-18.
In SSMII mode, received data comes from the PHY one bit at a time on
MII_RXD[0] (SSMII_RXD) on the rising edge of CLK_MII_RX
. MII_RXD[1]
(SSMII_RX_SYNC) indicates 10-bit segment alignment of the serial data stream.
MII_RX_DV
I
MII Receive Data Valid Input
In MII mode, this pin serves as the receive data valid input. In RMII mode, carrier
sense and receive data valid alternate on this pin. See the RMII spec for details. In
SSMII mode this pin is not used and should be pulled low or high.
MII_RX_ERR
I
MII Receive Error Input
In MII mode and RMII mode, this pin serves as the receive error input. In SSMII
mode this pin is not used and should be pulled low or high.
MII_COL
I
MII Collision Input
In MII mode this pin serves as the collision detection input. In RMII mode and
SSMII mode this pin is not used and should be pulled low or high.
MII_CRS
I
MII Carrier Sense Input
In MII mode this pin serves as the carrier sense input. In RMII mode and SMII
mode this pin is not used and should be pulled low or high.
MDC
O
8mA
PHY Management Clock Output
This signal is the clock for the Ethernet PHY management interface, which
consists of MDC and MDIO. See the timing diagram in Figure 14-14.
MDIO
IOpu
8mA
PHY Management Data Input/Output
This signal is the serial data signal for the Ethernet PHY management interface,
which consists of MDC
and MDIO. When MDIO is an output, it is updated on the
rising edge of MDC. When MDIO is an input, it is latched into the device on the
rising edge of MDC. See the timing diagram in Figure 14-14.
Table 9-5. Global Clock Pins
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
CLK_SYS_S
Ipd
System Clock Selection Input
This pin specifies the frequency of the clock applied to the CLK_SYS pin. See
section 10.4.
0 = 50 or 75 MHz
1 = 25 MHz
CLK_SYS
I
System Clock Input
A 25 MHz, 50 MHz or 75 MHz clock (±50 ppm or better) must be applied to this pin
to clock TDM-over-Packet internal circuitry and the SDRAM interface (SD_CLK).
When a 25MHz clock is applied, it is internally multiplied by the CLAD2 block to
50MHz or 75MHz as specified by GCR1.SYSCLKS. The CLK_SYS_S
pin specifies
whether the CLK_SYS signal is 25MHz (and therefore needs to multiplied up) or
50/75MHz (and therefore is used as-is). See section 10.4.
CLK_CMN
I
Common Clock Input
When the TDMoP engine is configured for common clock mode (also known as
differential mode), the common clock is applied to this pin. This clock signal has to
be a multiple of 8kHz and in the range of 1MHz to 25MHz. The frequency should
not be too close to an integer multiple of the service clock frequency. Based on
these criteria, the following frequencies are suggested:
For systems with access to a common SONET/SDH network, a frequency of 19.44
MHz (2430*8 kHz).
For systems with access to a common ATM network, 9.72 MHz (1215*8 kHz) or