Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 23 of 198
Table 9-4. Ethernet PHY Interface Pins (MII/RMII/SSMII)
The PHY interface type is configured by General_cfg_reg0.MII_mode_select[1:0]. 00=MII, 01=Reduced MII (RMII), 11=Source Synchronous
Serial MII (SSMII). The MII interface is described in IEEE 802.3-2005 Section 22. The RMII interface is described in this document:
http://www.national.com/appinfo/networks/files/rmii_1_2.pdf. The Source Synchronous Serial MII is described in this document:
ftp://ftp-eng.cisco.com/smii/smii.pdf.
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
CLK_MII_TX
I
MII Transmit Clock Input
In MII mode a 25MHz clock must be applied to this pin to clock the transmit side of
the interface. MII_TXD[3:0], MII_TX_EN and MII_TX_ERR are clocked out of the
device on the rising edge of CLK_MII_TX. See the timing diagram in
Figure 14-15.
In RMII mode a 50MHz clock must be applied to this pin to clock the transmit side
of the interface. MII_TXD[3:2] and MII_TX_EN are clocked out of the device on the
rising edge of CLK_MII_TX. See the timing diagram in
Figure 14-17.
In SSMII mode, a 125MHz clock must be applied to this pin. This clock is the
reference for the CLK_SSMII_TX output.
CLK_SSMII_TX
O
12ma
SSMII Transmit Clock Output
In SSMII mode, the device provides a 125MHz clock on this pin to clock the
transmit side of the interface. MII_TXD[0] (SSMII_TXD) and MII_TXD[1]
(SSMII_TX_SYNC) are clocked out of the device on the rising edge of
CLK_MII_TX. See the timing diagram in Figure 14-19
. This pin is not used in MII
and RMII modes.
MII_TXD[3:0]
O
8mA
MII Transmit Data Outputs
In MII mode, transmit data is passed to the PHY four bits at a time on
MII_TXD[3:0] on the rising edge of CLK_MII_TX. See the timing diagram in
Figure 14-15.
In RMII mode, transmit data is passed to the PHY two bits at a time on
MII_TXD[3:2] on the rising edge of CLK_MII_TX while MII_TXD[1:0] are not used.
See the timing diagram in
Figure 14-17.
In SSMII mode, transmit data is passed to the PHY one bit at a time on MII_TXD[0]
(SSMII_TXD) on the rising edge of CLK_SSMII_TX
. MII_TXD[1]
(SSMII_TX_SYNC) indicates 10-bit segment alignment of the serial data stream.
MII_TX_EN
O
8mA
MII Transmit Enable Output
In MII mode and RMII, this pin serves as the transmit enable output. In SSMII
mode this pin is not used.
MII_TX_ERR
O
8mA
MI Transmit Error Output
In MII mode this pin serves as the transmit error output. In RMII and SSMII modes
this pin is not used.
CLK_MII_RX
I
MII Receive Clock Input
In MII mode a 25MHz clock must be applied to this pin. MII_RXD[3:0], MII_RX_DV,
and MII_RX_ERR are clocked into the device on the rising edge of CLK_MII_RX.
See the timing diagram in Figure 14-16.
In RMII mode this pin is not used, and a 50MHz clock applied to CLK_MII_TX
provides timing for both transmit and receive sides of the interface. MII_RXD[3:2],
MII_RX_DV and MII_RX_ERR are clocked into the device on the rising edge of
CLK_MII_TX. See the timing diagram in Figure 14-18.
In SSMII mode a 125MHz clock from the PHY must be applied to this pin.
MII_RXD[0] (SSMII_RXD) and MII_RXD[1] (SSMII_RX_SYNC) are clocked into
the device on the rising edge of CLK_MII_RX. See the timing diagram in
Figure 14-20.