Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 22 of 198
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
TDMoP Request To Send Input
When the interface type is configured for serial, the request-to-send function of this
pin is active. In this mode, the real-time status of this pin can be read from
Port[n]_stat_reg1.RTS_P.
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
Port[n]_cfg_reg.Int_type specifies serial (00), E1 (01) or T1 (10) interface type.
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
Table 9-3. SDRAM Interface Pins
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
SD_CLK
O
8mA
SDRAM Clock
All SDRAM interface pins are updated or latched on the rising edge of SD_CLK.
See the timing diagrams in Figure 14-6 and Figure 14-7.
SD_D[31:0]
IO
8mA
SDRAM Data
MSB is SD_D[31].
SD_DQM[3:0]
O
8mA
SDRAM Byte Enable Mask
SD_DQM[0] is associated with the least significant byte. SD_DQM[3] is associated
with the most significant byte. When a SD_DQM pin is high during a write cycle,
the associated byte is not written to SDRAM. When a SD_DQM pin is high during
a read cycle, the associated byte is not driven out of the SDRAM (the SD_D
pins
remain high-Z).
SD_A[11:0]
O
8mA
SDRAM Address Bus
MSB is SD_A[11].
SD_BA[1:0]
O
8mA
SDRAM Bank Select Outputs
The external SDRAMs used by the device have their memory organized into four
banks. These pins specify the bank to be accessed. The bank must be specified
on the same SD_CLK edge that the row information is specified on SD_A[11:0].
SD_CS_N
O
8mA
SDRAM Chip Select (Active Low)
Driven low by the device to initiate a memory access (read or write) to the external
SDRAM.
SD_WE_N
O
8mA
SDRAM Write Enable (Active Low)
Driven low by the device when data is to be written to the external SDRAM. Left
high when data is to be read from the external SDRAM.
SD_RAS_N
O
8mA
SDRAM Row Address Strobe (Active Low)
Driven low by the device during SD_CLK cycles in which SD_A[11:0] indicates the
SDRAM row address.
SD_CAS_N
O
8mA
SDRAM Column Address Strobe (Active Low)
Driven low by the device during SD_CLK cycles in which SD_A[11:0] indicates the
SDRAM column address.