Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 21 of 198
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
Port[n]_cfg_reg.Int_type=specifies serial (00), E1 (01) or T1 (10).
Port[n]_cfg_reg.Int_type=specifies serial (00), E1 (01) or T1 (10) interface type.
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMn_TSIG_CTS
O
8mA
TDMoP Transmit Signaling Output
When the interface type is configured for E1 or T1, the transmit signaling function
of this pin is active. Functional timing is shown in Figure 10-33 and Figure 10-34.
TDMoP Clear to Send Output
When the interface type is configured for serial, the clear-to-send function of this
pin is active. In this mode, the state of this pin is controlled by the value stored in
Port[n]_cfg_reg.CTS.
Port[n]_cfg_reg.Int_type specifies serial (00), E1 (01) or T1 (10) interface type.
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMn_RCLK
Ipu
TDMoP Receive Clock Input
In two-clock mode, this signal clocks the receive TDM interface of the TDMoP
engine: TDMn_RX, TDMn_RX_SYNC and TDMn_RSIG_RTS.
In one-clock mode, this signal is ignored, and the TDMn_TCLK signal clocks both
the transmit and receive interfaces of the TDMoP engine.
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
Port[n]_cfg_reg.Rx_sample specifies latching on the rising (1) or falling (0) edge.
TDM1_RCLK (port 1) is used in high speed E3/T3/STS1 mode.
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMn_RX
Ipu
TDMoP Receive Data Input
Serial data to the TDMoP engine is input on this pin.
In two-clock mode, this signal is clocked by TDMn_RCLK.
In one-clock mode, this signal, is clocked by TDMn_TCLK.
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
TDM1_RX (port 1) is used in high speed E3/T3/STS1 mode.
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMn_RX_SYNC
Ipd
TDMoP Receive Frame/Multiframe Sync Input
In two-clock mode, this signal is clocked by TDMn_RCLK and specifies frame or
multiframe alignment for the receive interface of the TDMoP engine. The signal on
this pin must pulse high for one TDMn_RCLK cycle when the first bit of a frame is
present on the TDMn_RX pin. This pulse must be repeated every N*125µs where
N is a positive integer (example: if N=16, it pulses every 2ms).
In one-clock mode, this signal is ignored and TDMn_TX_SYNC specifies frame
alignment for both the transmit and receive interfaces of the TDMoP engine.
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMn_RSIG_RTS
Ipu
TDMoP Receive Signaling Input
When the interface type is configured for E1 or T1, the transmit signaling function
of this pin is active.
In two-clock mode, this signal is clocked by TDMn_RCLK.
In one-clock mode, this signal, is clocked by TDMn_TCLK.