Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 20 of 198
9.2 Detailed Pin Descriptions
Table 9-2. TDM-over-Packet Engine TDM Interface Pins
In this table, the transmit direction is the packet-to-TDM direction while the receive direction is the TDM-to-packet direction. See Figure 6-1.
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
TDMn_ACLK
O
8mA
TDMoP Recovered Clock Output
The clock recovered by the TDMoP clock recovery machine is output on this pin.
TDM1_ACLK (port 1) is used in high speed E3/T3/STS1 mode.
TDMn_TCLK
Ipu
TDMoP Transmit Clock Input
This signal clocks the transmit TDM interface of the TDMoP engine. Depending on
the value of Port[n]_cfg_reg:tx_sample, outputs TDMn_TX and TDMn_TSIG_CTS
are updated on the either the rising edge (0) or falling edge (1) of TDMn_TCLK.
Inputs TDMn_TX_SYNC and TDMn_TX_MF_CD are latched on the opposite
edge. See the timing diagrams in Figure 14-8 and Figure 14-9.
In one-clock mode, TDMn_TCLK also clocks the receive TDM interface of the
TDMoP engine. Depending on the value of Port[n]_cfg_reg:tx_sample, outputs
TDMn_RX, TDMn_RX_SYNC and TDMn_RSIG_RTS are updated on the either
the rising edge (0) or falling edge (1) of TDMn_TCLK.
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
This pin is only active in external mode (GCR1.MODE=1).
Only TDM1_TCLK (port 1) is used in high speed E3/T3/STS1 mode
(General_cfg_reg0.High_speed=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMn_TX
O
8mA
TDMoP Transmit Data Output
Serial data from the TDMoP engine is output on this pin.
This signal is clocked by TDMn_TCLK.
Only TDM1_TX (port 1) is used in high speed E3/T3/STS1 mode (i.e. when
General_cfg_reg0.High_speed=1).
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMn_TX_SYNC
Ipd
TDMoP Transmit Frame Sync Input
Frame sync information is provided to the TDMoP engine from this pin. In two-
clock mode, this signal specifies only transmit frame sync. In one-clock mode, this
signal specifies frame sync for both the transmit and receive directions.
The signal on this pin must pulse high for one TDMn_TCLK cycle when the first bit
of a frame is expected to present on the TDMn_TX pin (and the TDMn_RX pin in
one-clock mode). This pulse must be repeated every N*125µs where N is a
positive integer (example: if N=16, it pulses every 2ms).
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMn_TX_MF_CD
IOpd
TDMoP Transmit Multiframe Sync Input
When the interface type is configured for E1 or T1, multiframe sync is provided to
the TDMoP engine from this pin. The signal on this pin must pulse high for one
TDMn_TCLK cycle when the first bit the multiframe is expected to be present on
the TDMn_TX pin.
TDMoP Transmit Carrier Detect Output
When the interface type is configured for serial, the carrier detect function of this
pin is active. When Port[n]_cfg_reg
.CD_en=1, the state of this pin is controlled by
the value stored in Port[n]_cfg_reg.CD.