Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 2 of 198
Table of Contents
1. INTRODUCTION ................................................................................................................................. 7
2. ACRONYMS AND GLOSSARY .......................................................................................................... 8
3. APPLICABLE STANDARDS ............................................................................................................ 10
4. DETAILED DESCRIPTION ............................................................................................................... 11
5. APPLICATION EXAMPLES .............................................................................................................. 12
6. BLOCK DIAGRAM ............................................................................................................................ 14
7. FEATURES ....................................................................................................................................... 15
8. OVERVIEW OF MAJOR OPERATIONAL MODES ........................................................................... 17
9. PIN DESCRIPTIONS ......................................................................................................................... 18
9.1 SHORT PIN DESCRIPTIONS.............................................................................................................. 18
9.2 DETAILED PIN DESCRIPTIONS ......................................................................................................... 20
10. FUNCTIONAL DESCRIPTION ........................................................................................................ 28
10.1 POWER-SUPPLY CONSIDERATIONS ............................................................................................... 28
10.2 CPU INTERFACE .......................................................................................................................... 28
10.3 SPI INTERFACE ............................................................................................................................ 31
10.3.1 SPI Operation .................................................................................................................................... 31
10.3.2 SPI Modes ......................................................................................................................................... 32
10.3.3 SPI Signals ........................................................................................................................................ 33
10.3.4 SPI Protocol ....................................................................................................................................... 33
10.4 CLOCK STRUCTURE ...................................................................................................................... 36
10.5 RESET AND POWER-DOWN ........................................................................................................... 37
10.6 TDM-OVER-PACKET BLOCK .......................................................................................................... 37
10.6.1 Packet Formats .................................................................................................................................. 37
10.6.2 Typical Application ............................................................................................................................. 47
10.6.3 Clock Recovery .................................................................................................................................. 48
10.6.4 Timeslot Assigner (TSA) ..................................................................................................................... 49
10.6.5 CAS Handler ...................................................................................................................................... 50
10.6.6 AAL1 Payload Type Machine ............................................................................................................. 54
10.6.7 HDLC Payload Type Machine............................................................................................................. 57
10.6.8 RAW Payload Type Machine .............................................................................................................. 58
10.6.9 SDRAM and SDRAM Controller ......................................................................................................... 62
10.6.10 Jitter Buffer Control (JBC) ................................................................................................................. 63
10.6.11 Queue Manager ............................................................................................................................... 66
10.6.12 Ethernet MAC................................................................................................................................... 78
10.6.13 Packet Classifier .............................................................................................................................. 81
10.6.14 Packet Trailer Support ...................................................................................................................... 84
10.6.15 Counters and Status Registers ......................................................................................................... 85
10.6.16 Connection Level Redundancy ......................................................................................................... 85
10.6.17 OAM Signaling ................................................................................................................................. 86
10.7 GLOBAL RESOURCES ................................................................................................................... 87
10.8 PER-PORT RESOURCES................................................................................................................ 87
10.9 DEVICE INTERRUPTS .................................................................................................................... 87
11. DEVICE REGISTERS...................................................................................................................... 89
11.1 ADDRESSING................................................................................................................................ 89
11.2 TOP-LEVEL MEMORY MAP ............................................................................................................ 90