Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 198 of 198
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19. Data Sheet Revision History
REVISION
DATE
DESCRIPTION
071108
Initial release.
100108
In the Ordering Information table on page 1, removed the asterisks and footnotes that indicated
DS34S101, DS34S102 and DS34S104 were future products.
In Table 11-11, Table 11-13, Table 11-14 and Table 11-15, corrected the index variable in the
Description column from n to ts to match the other columns.
Updated Figure 6-1 to show all CPU interface pins including SPI bus pin names.
In section 11.4.8, changed the index into the jitter buffer control registers from j = 0 to 255 to port
= 1 to 8 and ts = 0 to 31 for additional clarity.
101408
Removed all references to AAL2 mode.
Replaced the incorrect terms “cell” and “cells” with “AAL1 SAR PDU” throughout the document
except in register names and register field names.
Edited section 10.6.6 for additional clarity about the AAL1 mapping methods.
Corrected some spelling errors and other minor typos.
In Table 9-1, change note on TST_CLD pin from “DS34S104 only” to “DS34S108 only”.
Corrected Table 16-1, which previously was missing a large section from the middle.
Added future status for DS34S101 and DS34S102 to the Ordering Information table.
032609
Removed future status for the DS34S101 and DS34S102 in the Ordering Information table.