Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 182 of 198
15.4.2 Connecting the H_READY_N Signal
The H_READY_N output should be connected to the MPC860 TA input. The CPU bus operates asynchronously.
The TA of the MPC860 is a synchronous input (i.e., needs to meet set-up and hold times). The designer should
synchronize H_READY_N to the MPC860 clock by means of a CPLD, which uses the MPC860 reference clock.
The internal logic in the CPLD also uses the MPC860 CS (chip select) output. Both the H_READY_N output and
the MPC860 TA input should have a 1kΩ pull-up resistor.
Figure 15-11. Connecting the H_READY_N Signal to the MPC860 TA Pin
Figure 15-12. Internal CPLD Logic to Synchronize H_READY_N to the MPC860 Clock
Another alternative for connecting the H_READY_N signal is using the MPC860 UPM. In this option the
H_READY_N output should be connected to the MPC860 UPWAIT (GPL4) signal, and no external timing
adjustment is needed. The H_READY_N output should have a 1kΩ pull-up resistor. Refer to the MPC860 user
manual for additional details.
MPC860
DS34S108
TA
H_READY_N
VCC
1K
CPLD
CS
H_CS_N
CLKOUT
R/W
H_R_W_N
VCC
1K