Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 174 of 198
Figure 14-19. SSMII Interface Output Signal Timing
CLK_SSMII_TX
MII_TXD_0(SSMII_TXD)
MII_TXD_1(SSMII_TX_SYNC)
T172
T171 T189
T172
Figure 14-20. SSMII Interface Input Signal Timing
CLK_MII_RX(CLK_SSMII_RX)
MII_RXD_0(SSMII_RXD)
MII_RXD_1(SSMII_RX_SYNC)
T176
T171
T175 T176
T175
T189
NOTES FOR SECTION 14.5:
1. The output timing specified for MII/RMII/SSMII interfaces assumes 20pf load for MII_TXD[3:0], MII_TX_EN, and MII_TX_ERR.
2. The output timing specified for MII/RMII/SSMII interfaces assumes 30pf load for MDC and MDIO.
3. The output timing specified for SSMII interface assumes 25pf load for CLK_SSMII_TX.
14.6 CLAD and System Clock Timing
Table 14-14. CLAD1 and CLAD2 Input Clock Specifications
PARAMETER
MIN
TYP
MAX
UNITS
ACCURACY
CLK_SYS Frequency
25 or 50
MHz
±50ppm
CLK_SYS Duty Cycle
40
60
%
CLK_HIGH Frequency
10.00
19.44
38.88
77.76
MHz
Traceable to
Stratum 3E or higher
CLK_HIGH Duty Cycle
40
60
%
MCLK Frequency
1.544
2.048
MHz
±32ppm
±50ppm
MCLK Duty Cycle
40
60
%
CLK_SYS Frequency
25
50
75
MHz
±50ppm
CLK_SYS Duty Cycle
40
60
%