Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 169 of 198
14.4 TDM-over-Packet TDM Interface Timing
Table 14-5. TDMoP TDM Interface AC Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TDMn_TX_SYNC, TDMn_TX_MF_CD, TDMn_RX,
TDMn_RX_SYNC, TDMn_RSIG_RTS Input Setup Prior
to TDMn_TCLK for E1/T1/Serial Interface
T101
1.8
ns
TDMn_TX_SYNC, TDMn_TX_MF_CD, TDMn_RX,
TDMn_RX_SYNC, TDMn_RSIG_RTS Input Hold After
TDMn_TCLK for E1/T1/Serial Interface
T102
1.1
ns
TDMn_TCLK to TDMn_TX, TDMn_TSIG_CTS Output
Hold for E1/T1/Serial Interface
T103
2.8
ns
TDMn_TCLK to TDMn_TX, TDMn_TSIG_CTS Output
Valid for E1/T1/Serial Interface
T104
13.3
ns
TDM1_TCLK to TDM1_TX Output Hold for High Speed
\Interface
T103
4.5
(Note 1)
ns
TDM1_TCLK to TDM1_TX Output Valid for High Speed
\Interface
T104
12.5
(Note 1)
ns
TDMn_RX, TDMn_RX_SYNC, TDMn_RSIG_RTS Input
Setup Prior to TDMn_RCLK for E1/T1/Serial Interface
T109
1.8
ns
TDMn_RX, TDMn_RX_SYNC, TDMn_RSIG_RTS Input
Hold After TDMn_RCLK for E1/T1/Serial Interface
T110
0
ns
TDM1_RX Input Setup Prior to TDM1_RCLK for High
Speed Interface
T109
1.8
ns
TDM1_RX Input Hold After TDM1_RCLK for High Speed
Interface
T110
1.1
ns
NOTES:
1. The output timing specified for TDM1_TX assumes 20 pF load.
Table 14-6. TDMoP TDM Clock AC Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TDMn_TCLK Frequency for E1 Interface
T100
2.048
MHz
TDMn_TCLK Frequency for T1 Interface
T100
1.544
MHz
TDMn_RCLK, TDMn_TCLK Frequency for Serial
Interface
T106
16k
4.65M
Hz
TDM1_RCLK, TDM1_TCLK Frequency for High Speed
Interface
T106
16k
51.84M
Hz
TDMn_RCLK, TDMn_TCLK Duty Cycle for 1/T1 Serial
Interface
T107
40
60
%
TDM1_RCLK, TDM1_TCLK Duty Cycle for High Speed
Interface
T107
40
60
%
NOTE: The output timing specified for TDM interfaces assumes 30 pF load.
Figure 14-8. TDMoP TDM Timing, One-Clock Mode (Two_clocks=0, Tx_sample=1)
TDMn_TCLK
DMn_RX,TDMn_RSIG_RTS,TDMn_RX_SYNC
TDMn_TX_MF_CD,T DMn_TX_SYNC
TDMn_TX,TDMn_TSIG_CTS
T100
T101
T102
T101
T102
T103
T104