Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 155 of 198
Alignment_errors 0x054
Bits Data Element Name R/W
Reset
Value
Description
[31:8]
Reserved
-
0x0
Must be set to zero
[7:0]
Alignment_errors
R/W
0x0
An 8-bit register counting packets that are not an integral
number of bytes long and have bad CRC when their
length is truncated to an integral number of bytes and are
between 64 and 1518 bytes in length (2000 if
Rx_2000_byte_packets is set in the
MAC_network_configuration register).
Deferred_transmission_packets 0x058
Bits Data Element Name R/W
Reset
Value
Description
[31:16]
Reserved
-
0x0
Must be set to zero
[15:0]
Deferred_transmission_packets
R/W
0x0
A 16-bit register counting the number of packets
experiencing deferral due to carrier sense being active on
their first attempt at transmission. Packets involved in any
collision are not counted nor are packets that experienced
a transmit underrun.
Late_collisions 0x05C
Bits Data Element Name R/W
Reset
Value
Description
[31:8]
Reserved
-
0x0
Must be set to zero
[7:0]
Late_collisions
R/W
0x0
An 8-bit register counting the number of packets that
experience a collision after the slot time (512 bits) has
expired. A late collision is counted twice i.e. both as a
collision and a late collision.
Excessive_collisions 0x060
Bits Data Element Name R/W
Reset
Value
Description
[31:8]
Reserved
-
0x0
Must be set to zero
[7:0]
Excessive_collisions
R/W
0x0
An 8-bit register counting the number of packets that
failed to be transmitted because they experienced 16
collisions.
Transmit_underrun_errors 0x064
Bits Data Element Name R/W
Reset
Value
Description
[31:8]
Reserved
-
0x0
Must be set to zero
[7:0]
Transmit_underruns
R/W
0x0
An 8-bit register counting the number of packets not
transmitted due to a transmit FIFO underrun. If this
register is incremented, no other Ethernet MAC counter is
incremented.