Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 150 of 198
MAC_network_status 0x008
Bits Data Element Name R/W
Reset
Value
Description
[31:3]
Reserved
-
0x0
Must be set to zero
[2]
PHY_access_has_completed
RO
0x1
1 = PHY management logic is idle.
[1:0]
Reserved
-
0x0
Must be set to zero
MAC_transmit_status 0x014
Bits Data Element Name R/W
Reset
Value
Description
[31:7]
Reserved
-
0x0
Must be set to zero
[6]
Transmit_underrun
R/W
0x0
Set when the MAC transmit FIFO was read while was
empty. If this happens the transmitter forces bad CRC and
forces MII_TX_ERR high. Write 1 to clear this bit.
[5:3]
Reserved
-
0x0
Must be set to zero
[2]
Retry_limit_exceeded
R/W
0x0
Set when the retry limit has been exceeded. Write 1 to
clear this bit.
[1]
Collision_occurred
R/W
0x0
Set when a collision occurs. Write 1 to clear this bit.
[0]
Reserved
-
0x0
Must be set to zero
The MAC generates a single interrupt, the ETH_MAC bit in the Intpend register. The MAC_interrupt_status register
below indicates the source of this interrupt. For test purposes each bit can be set or reset by directly writing to this
register regardless of the state of the mask register. Otherwise the corresponding bit in the MAC_interrupt_mask
register must be cleared for a bit to be set in the MAC_interrupt_status register. All bits are reset to zero on read. If
any bit is set in the MAC_interrupt_status register, the ETH_MAC bit is asserted.
At reset all MAC interrupts are disabled. Writing a one to the relevant bit location in the MAC_interrupt_enable
register below enables the associated interrupt. Writing a one to the relevant bit location in the
MAC_interrupt_disable register below disables the associated interrupt. MAC_interrupt_enable and
MAC_interrupt_disable are not registers but merely mechanisms for setting and clearing bits in the read-only
MAC_interrupt_mask register.
MAC_interrupt_status 0x024
Bits Data Element Name R/W
Reset
Value
Description
[31:14]
Reserved
RO
0x0
Read 0, ignored on write
[13]
Pause_time_zero
R/W
0x0
Set when the MAC_pause_time register decrements to
zero. Cleared when read.
[12]
Pause_packet_ Rxd
R/W
0x0
Indicates a valid pause packet has been received.
Cleared when read.
[11:6]
Reserved
0x0
Must be set to zero
[5]
Retry_limit_exceeded
R/W
0x0
Transmit error. Cleared when read.
[4]
Ethernet_transmit_underrun
R/W
0x0
Set when the MAC transmit FIFO was read while was
empty. If this happens the transmitter forces bad CRC and
forces MII_TX_ERR high. Cleared when read.
[3:1]
Reserved
0x0
Must be set to zero
[0]
Management_packet_sent
R/W
0x0
The PHY maintenance register has completed its
operation. Cleared when read.
MAC_interrupt_enable 0x028
Bits Data Element Name R/W
Reset
Value
Description
[31:14]
Reserved
-
0x0
Must be set to zero
[13]
Pause_time_zero
WO
0x0
1 = Enable Pause_time_zero interrupt
[12]
Pause_packet_ Rxd
WO
0x0
1 = Enable Pause_packet_Rxd interrupt
[11:6]
Reserved
-
0x0
Must be set to zero