Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 146 of 198
CPU_Queues_mask 0x1C4
Bits Data Element Name R/W
Reset
Value
Description
[31:10]
Reserved
-
0x0
Must be set to zero
[9]
TDM_to_CPU_pool_thresh
R/W
0x1
Mask TDM_to_CPU_pool_thresh interrupts
[8]
TDM_to_CPU_q_thresh
R/W
0x1
Mask TDM_to_CPU_q_thresh interrupts
[7]
CPU_to_ETH_q_thresh
R/W
0x1
Mask CPU_to_ETH_q_thresh interrupts
[6]
ETH_to_CPU_pool_thresh
R/W
0x1
Mask ETH_to_CPU_pool_thresh interrupts
[5]
ETH_to_CPU_q_thresh
R/W
0x1
Mask ETH_to_CPU_q_thresh interrupts
[4:3]
Reserved
R/W
0x1
Must be set to zero
[2]
CPU_to_TDM_q_thresh
R/W
0x1
Mask CPU_to_TDM_q_thresh interrupts
[1]
Tx_return_q_thresh
R/W
0x1
Mask Tx_return_q_thresh interrupts
[0]
Rx_return_q_thresh
R/W
0x1
Mask Rx_return_q_thresh interrupts