Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 144 of 198
Tx_CAS_change 0xC0+(port-1)*8
Bits Data Element Name R/W
Reset
Value
Description
[31:0]
Tx_CAS_change
R/W
0x0000
0000
Bit 31 represents timeslot 31 and bit 0 represents timeslot
0 for the port. When a bit is set it indicates a change in
transmit (toward the Ethernet port) CAS bits in the
corresponding timeslot. The current CAS bits can be read
from the signaling registers in the neighboring framer IC.
See section 10.6.5.1.
Tx_CAS_change_mask 0xC4+(port-1)*8
Bits Data Element Name R/W
Reset
Value
Description
[31:0]
Tx_CAS_change_maxk
R/W
0xFFFF
FFFF
Each bit masks interrupts caused by the corresponding bit
in the Tx_CAS_change register. See section 10.6.5.1.
RTS_change 0x100
Bits Data Element Name R/W
Reset
Value
Description
[31:8]
Reserved
-
0x0
Must be set to zero
[7]
RTS8_ change
R/W
0x0
TDM8_RTS input level changed.
[6]
RTS7_ change
R/W
0x0
TDM7_RTS input level changed.
[5]
RTS6_ change
R/W
0x0
TDM6_RTS input level changed.
[4]
RTS5_ change
R/W
0x0
TDM5_RTS input level changed.
[3]
RTS4_ change
R/W
0x0
TDM4_RTS input level changed.
[2]
RTS3_ change
R/W
0x0
TDM3_RTS input level changed.
[1]
RTS2_ change
R/W
0x0
TDM2_RTS input level changed.
[0]
RTS1_ change
R/W
0x0
TDM1_RTS input level changed.
RTS_mask 0x104
Bits Data Element Name R/W
Reset
Value
Description
[31:8]
Reserved
-
0x0
Must be set to zero
[7:0]
RTS_mask
R/W
0xFF
Each bit masks interrupts caused by the corresponding bit
in the RTS_change register.
CW_bits_change_low_bundles 0x140
Bits Data Element Name R/W
Reset
Value
Description
[31:0]
CW_bits_change
R/W
0xFFFF
FFFF
Bit 31 represents bundle 31 and bit 0 represents bundle 0.
When a bit is set it indicates the corresponding bundle
had a change in one of the bundle’s control word fields: L,
R, M or FRG. The CW_bits_change_mask register
specifies which of the four Control Word fields can cause
an interrupt when changed. The current state of the four
fields can be read from the Packet Classifier Status
register in the per-bundle status tables (section 11.4.4.1).
CW_bits_mask_low_bundles 0x144
Bits Data Element Name R/W
Reset
Value
Description
[31:0]
CW_bits_mask
R/W
0xFFFF
FFFF
Bit 31 represents bundle 31 and bit 0 represents bundle 0.
Mask the interrupt from the corresponding bit in the