Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 142 of 198
Intpend 0x000
Bits Data Element Name R/W
Reset
Value
Description
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
[15]
JBC_underrun_P8
R/W
0x0
One of the Port8 Jitter Buffers is in underrun state.
Read the Port8 JBC_underrun register to determine the
interrupt source(s).
[14]
JBC_underrun_P7
R/W
0x0
One of the Port7 Jitter Buffers is in underrun state.
Read the Port7 JBC_underrun register to determine the
interrupt source(s).
[13]
JBC_underrun_P6
R/W
0x0
One of the Port6 Jitter Buffers is in underrun state.
Read the Port6 JBC_underrun register to determine the
interrupt source(s).
[12]
JBC_underrun_P5
R/W
0x0
One of the Port5 Jitter Buffers is in underrun state.
Read the Port5 JBC_underrun register to determine the
interrupt source(s).
[11]
JBC_underrun_P4
R/W
0x0
One of the Port4 Jitter Buffers is in underrun state.
Read the Port4 JBC_underrun register to determine the
interrupt source(s).
[10]
JBC_underrun_P3
R/W
0x0
One of the Port3 Jitter Buffers is in underrun state.
Read the Port3 JBC_underrun register to determine the
interrupt source(s).
[9]
JBC_underrun_P2
R/W
0x0
One of the Port2 Jitter Buffers is in underrun state.
Read the Port2 JBC_underrun register to determine the
interrupt source(s).
[8]
JBC_underrun_P1
R/W
0x0
One of the Port1 Jitter Buffers is in underrun state.
Read the Port1 JBC_underrun register to determine the
interrupt source(s).
[7]
Rx_CAS_change_P8
R/W
0x0
A change has occurred in Port8 Receive Line CAS table.
Read the Port8 Rx_CAS_change register to determine the
interrupt source(s).
[6]
Rx_CAS_change_P7
R/W
0x0
A change has occurred in Port7 Receive Line CAS table.
Read the Port7 Rx_CAS_change register to determine the
interrupt source(s).
[5]
Rx_CAS_change_P6
R/W
0x0
A change has occurred in Port6 Receive Line CAS table.
Read the Port6 Rx_CAS_change register to determine the
interrupt source(s).
[4]
Rx_CAS_change_P5
R/W
0x0
A change has occurred in Port5 Receive Line CAS table.
Read the Port5 Rx_CAS_change register to determine the
interrupt source(s).
[3]
Rx_CAS_change_P4
R/W
0x0
A change has occurred in Port4 Receive Line CAS table.
Read the Port4 Rx_CAS_change register to determine the
interrupt source(s).
[2]
Rx_CAS_change_P3
R/W
0x0
A change has occurred in Port 3 Receive Line CAS table.
Read the Port3 Rx_CAS_change register to determine the
interrupt source(s).
[1]
Rx_CAS_change_P2
R/W
0x0
A change has occurred in Port 2 Receive Line CAS table.
Read the Port2 Rx_CAS_change register to determine the
interrupt source(s).
[0]
Rx_CAS_change_P1
R/W
0x0
A change has occurred in Port 1 Receive Line CAS table.
Read the Port1 Rx_CAS_change register to determine the
interrupt source(s).
Intmask 0x004
Bits Data Element Name R/W
Reset
Value
Description
[31:28]
Reserved
-
0x0
Must be set to zero
[27]
ETH_MAC
R/W
0x1
Mask Ethernet MAC interrupt.
[26]
CPU Queues
R/W
0x1
Mask CPU Queues change interrupt.