Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 141 of 198
Addr
Offset
Register Name Description Page
0x0E4
Tx_CAS_change_mask_P5
Tx CAS change mask for Port 1
144
0x0EC
Tx_CAS_change_mask_P6
Tx CAS change mask for Port 1
144
0x0F4
Tx_CAS_change_mask_P7
Tx CAS change mask for Port 1
144
0x0FC
Tx_CAS_change_mask_P8
Tx CAS change mask for Port 1
144
0x100
RTS_change
RTS change register for Ports 1 to 8
144
0x104
RTS_mask
RTS change mask for Ports 1 to 8
144
0x140
CW_bits_change_low_bundles
CW bits change for bundles 0 to 31
144
0x144
CW_bits_mask_low_bundles
CW bits change mask for bundles 31 to 0
144
0x148
CW_bits_change_high_bundles
CW bits change for bundles 32 to 63
145
0x14C
CW_bits_mask_high_bundles
CW bits change mask for bundles 63 to 32
145
0x180
CW_bits_change_mask
Which CW fields (L, R, M, FRG) cause interrupts on change
145
0x1C0
CPU_Queues_change
Which CPU pools and queues went above/below thresholds
145
0x1C4
CPU_Queues_mask
CPU Queues changed mask
146
Intpend 0x000
Bits Data Element Name R/W
Reset
Value
Description
[31:28]
Reserved
-
0x0
Must be set to zero
[27]
ETH_MAC
R/W
0x0
Ethernet MAC interrupt. Read the MAC_interrupt_status
register to determine the interrupt source(s).
[26]
CPU Queues
R/W
0x0
The fill level of one or more of the CPU queues and pools
has gone beyond the configured threshold. Read the
CPU_Queues_change register to determine the interrupt
source(s).
[25]
CW_bits_change
R/W
0x0
At least one of the L, R, M or FRG control Word fields has
changed in one or more bundles. Read the
CW_bits_change_low_bundles and
CW_bits_change_high_bundles registers to determine the
interrupt source(s).
The CW_bits_change_mask
register indicates which of
the four CW fields can cause an interrupt when changed.
[24]
RTS_changes
R/W
0x0
1 = The state of the RTS pin (TDMn_RSIG_RTS) for one
or more ports has changed. This only applies for port in
asynchronous serial interface mode (
Port[n]_cfg_reg.
Int_type=00). Read the RTS_change
register to determine
the interrupt source(s).
[23]
Tx_CAS_change_P8
R/W
0x0
A change has occurred in the CAS signaling bits for Port8.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
[22]
Tx_CAS_change_P7
R/W
0x0
A change has occurred in the CAS signaling bits for Port7.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
[21]
Tx_CAS_change_P6
R/W
0x0
A change has occurred in the CAS signaling bits for Port6.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
[20]
Tx_CAS_change_P5
R/W
0x0
A change has occurred in the CAS signaling bits for Port5.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
[19]
Tx_CAS_change_P4
R/W
0x0
A change has occurred in the CAS signaling bits for Port4.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
[18]
Tx_CAS_change_P3
R/W
0x0
A change has occurred in the CAS signaling bits for Port3.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
[17]
Tx_CAS_change_P2
R/W
0x0
A change has occurred in the CAS signaling bits for Port2.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
[16]
Tx_CAS_change_P1
R/W
0x0
A change has occurred in the CAS signaling bits for Port1.