Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 140 of 198
11.4.14 Interrupt Controller
The base address for the interrupt controller register space is 0x68,000.
The Intpend register and the “change” registers listed below have latched status bits that indicate various TDMoP
hardware events. For each bit, the value 1 indicates that the event occurred. Writing 1 to a bit clears it to 0. Writing
0 to a bit does not change its value.
The Intmask register and the other “mask” registers listed below have an interrupt mask bit corresponding to each
bit in the associated “change” register. Each mask bit masks the interrupt when set to 1 and does not mask the
interrupt when set to 0.
The Intpend register is the master interrupt status register. “Change” bits in Intpend indicate that one or more
events of a specific type have occurred. More details about which ports or bundles had that type of event can be
found by reading the change register(s) for that event type.
In the register descriptions in this section, the index port indicates port number: 1-8 for DS34S108, 1-4 for
DS34S104, 1-2 for DS34S102, 1 only for DS34S101.
Table 11-15. Interrupt Controller Registers
Addr
Offset
Register Name Description Page
0x000
Intpend
Interrupts pending register
141
0x004
Intmask
Interrupt mask register
142
0x040
Rx_CAS_change_P1
Rx CAS change for timeslots in Port 1
143
0x044
Rx_CAS_change_P2
Rx CAS change for timeslots in Port 2
143
0x048
Rx_CAS_change_P3
Rx CAS change for timeslots in Port 3
143
0x04C
Rx_CAS_change_P4
Rx CAS change for timeslots in Port 4
143
0x050
Rx_CAS_change_P5
Rx CAS change for timeslots in Port 5
143
0x054
Rx_CAS_change_P6
Rx CAS change for timeslots in Port 6
143
0x058
Rx_CAS_change_P7
Rx CAS change for timeslots in Port 7
143
0x05C
Rx_CAS_change_P8
Rx CAS change for timeslots in Port 8
143
0x080
JBC_underrun_P1
JBC underrun in Port 1.
143
0x088
JBC_underrun_P2
JBC underrun in Port 2
143
0x090
JBC_underrun_P3
JBC underrun in Port 3
143
0x098
JBC_underrun_P4
JBC underrun in Port 4
143
0x0A0
JBC_underrun_P5
JBC underrun in Port 5
143
0x0A8
JBC_underrun_P6
JBC underrun in Port 6
143
0x0B0
JBC_underrun_P7
JBC underrun in Port 7
143
0x0B8
JBC_underrun_P8
JBC underrun in Port 8
143
0x084
JBC_underrun_mask_P1
JBC underrun mask for Port 1
143
0x08C
JBC_underrun_mask_P2
JBC underrun mask for Port 2
143
0x094
JBC_underrun_mask_P3
JBC underrun mask for Port 3
143
0x09C
JBC_underrun_mask_P4
JBC underrun mask for Port 4
143
0x0A4
JBC_underrun_mask_P5
JBC underrun mask for Port 5
143
0x0AC
JBC_underrun_mask_P6
JBC underrun mask for Port 6
143
0x0B4
JBC_underrun_mask_P7
JBC underrun mask for Port 7
143
0x0BC
JBC_underrun_mask_P8
JBC underrun mask for Port 8
143
0x0C0
Tx_CAS_change_P1
Tx CAS change for timeslots in Port 1
144
0x0C8
Tx_CAS_change_P2
Tx CAS change for timeslots in Port 2
144
0x0D0
Tx_CAS_change_P3
Tx CAS change for timeslots in Port 3
144
0x0D8
Tx_CAS_change_P4
Tx CAS change for timeslots in Port 4
144
0x0E0
Tx_CAS_change_P5
Tx CAS change for timeslots in Port 5
144
0x0E8
Tx_CAS_change_P6
Tx CAS change for timeslots in Port 6
144
0x0F0
Tx_CAS_change_P7
Tx CAS change for timeslots in Port 7
144
0x0F8
Tx_CAS_change_P8
Tx CAS change for timeslots in Port 8
144
0x0C4
Tx_CAS_change_mask_P1
Tx CAS change mask for Port 1
144
0x0CC
Tx_CAS_change_mask_P2
Tx CAS change mask for Port 1
144
0x0D4
Tx_CAS_change_mask_P3
Tx CAS change mask for Port 1
144
0x0DC
Tx_CAS_change_mask_P4
Tx CAS change mask for Port 1
144