Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 14 of 198
6. Block Diagram
Figure 6-1. Top-Level Block Diagram
SD_D[31:0] SD_DQM[3:0] SD_A[11:0] SD_BA[1:0] SD_CLK SD_CS_N SD_WE_N SD_RAS_N SD_CAS_N
CLK_HIGH
CLK_CMN
TDMn_RCLK
TDMn_RX
TDMn_RSIG_RTS
TDMn_ACLK
TDMn_TX_SYNC
TDMn_RX_SYNC
TDMoP Block
all 8 ports
Clock
Recovery
Machines
Timeslot
Assigner
CAS
Handler
SDRAM
Controller
Jitter
Buffer
Control
Queue
Manager
Ethernet
MAC
10/100
Packet
Classifier
Counters
& Status
Registers
CPU
Interface
CLK_MII_RX
MII_RXD[3:0]
MII_RX_DV
MII_RX_ERR
MII_COL
MII_CRS
CLK_MII_TX
CLK_SSMII_TX
MII_TXD[3:0]
MII_TX_EN
MDIO
MDC
CLK_SYS
RST_SYS_N
JTAG
JTMS
JTCLK
JTDI
JTDO
JTRST_N
MII_TX_ERR
CLAD1
38.88MHz
2.048/1.544MHz
CLAD2
50 or 75MHz
CLK_SYS_S
Payload Type
Machines
AAL1
HDLC
SAToP
CESoPSN
RAW
SCEN
SCAN
MBIST
STMD
MBIST_EN
MBIST_DONE
MBIST_FAIL
HIZ_EN
Control
Bank Select
Address
Byte Enable Mask
Data
TDMn_TX
TDMn_TX_MF_CD
TDMn_TSIG_CTS
TDMn_TCLK
H_D[31:1]
H_AD[24:1]
H_CS_N
H_R_W_N
H_WR_BE[0]_N / SPI_CLK
H_READY_N
H_INT[1:0]
DATA_31_16_N
H_CPU_SPI_N
H_D[0] / SPI_MISO
H_WR_BE[1]_N / SPI_MOSI
H_WR_BE[2]_N / SPI_SEL_N
H_WR_BE[3]_N / SPI_CI