Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 138 of 198
11.4.12 Receive SW Conditioning Octet Select
The base address for the TDMoP Rx software conditioning octet select register space is 0x50,000. These registers
specify which of four conditioning bytes (TDM_cond_octet_a through TDM_cond_octet_d in TDM_cond_data_reg)
the TDMoP block transmits on the TDMn_TX signals during an unassigned timeslot. The specified value is also the
conditioning octet that is inserted into the jitter buffer for lost packet compensation.
In the register descriptions in this section, the index port indicates port number: 1-8 for DS34S108, 1-4 for
DS34S104, 1-2 for DS34S102, 1 only for DS34S101. The index ts indicates timeslot number: 0 to 31.
Table 11-13. Receive SW Conditioning Octet Select Registers
Addr
Offset
Register Name Description Page
Port 1
0x000
Rx_SW_cond_TS0
Rx software conditioning for timeslot 0 for Port 1
138
0x000+ts*4
Rx_SW_cond_TS[ts]
Rx software conditioning for timeslot ts for Port 1
138
0x07C
Rx_SW_cond_TS31
Rx software conditioning for timeslot 31 for Port 1
138
Port 2
0x080
Rx_SW_cond_TS0
Rx software conditioning for timeslot 0 for Port 2
138
0x080+ts*4
Rx_SW_cond_TS[ts]
Rx software conditioning for timeslot ts for Port 2
138
0x0FC
Rx_SW_cond_TS31
Rx software conditioning for timeslot 31 for Port 2
138
Port 3
0x100
Rx_SW_cond_TS0
Rx software conditioning for timeslot 0 for Port 3
138
0x100+ts*4
Rx_SW_cond_TS[ts]
Rx software conditioning for timeslot ts for Port 3
138
0x17C
Rx_SW_cond_TS31
Rx software conditioning for timeslot 31 for Port 3
138
Port 4
0x180
Rx_SW_cond_TS0
Rx software conditioning for timeslot 0 for Port 4
138
0x180+ts*4
Rx_SW_cond_TS[ts]
Rx software conditioning for timeslot ts for Port 4
138
0x1FC
Rx_SW_cond_TS31
Rx software conditioning for timeslot 31 for Port 4
138
Port 5
0x200
Rx_SW_cond_TS0
Rx software conditioning for timeslot 0 for Port 5
138
0x200+ts*4
Rx_SW_cond_TS[ts]
Rx software conditioning for timeslot ts for Port 5
138
0x27C
Rx_SW_cond_TS31
Rx software conditioning for timeslot 31 for Port 5
138
Port 6
0x280
Rx_SW_cond_TS0
Rx software conditioning for timeslot 0 for Port 6
138
0x280+ts*4
Rx_SW_cond_TS[ts]
Rx software conditioning for timeslot ts for Port 6
138
0x2FC
Rx_SW_cond_TS31
Rx software conditioning for timeslot 31 for Port 6
138
Port 7
0x300
Rx_SW_cond_TS0
Rx software conditioning for timeslot 0 for Port 7
138
0x300+ts*4
Rx_SW_cond_TS[ts]
Rx software conditioning for timeslot ts for Port 7
138
0x37C
Rx_SW_cond_TS31
Rx software conditioning for timeslot 31 for Port 7
138
Port 8
0x380
Rx_SW_cond_TS0
Rx software conditioning for timeslot 0 for Port 8
138
0x380+ts*4
Rx_SW_cond_TS[ts]
Rx software conditioning for timeslot ts for Port 8
138
0x3FC
Rx_SW_cond_TS31
Rx software conditioning for timeslot 31 for Port 8
138
Rx_SW_cond 0x000+(port-1)*0x80+ts*4
Bits Data Element Name R/W
Reset
Value
Description
[31:2]
Reserved
-
0x0
Must be set to zero
[1:0]
Cond_octet_sel
R/W
None
00 = TDM_cond_octet_a
01 = TDM_cond_octet_b
10 = TDM_cond_octet_c
11 = TDM_cond_octet_d