Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 136 of 198
11.4.10 Receive Line CAS
The base address for the TDMoP Rx line CAS register space is 0x40,000. These read-only registers allow the CPU
to examine the state of the CAS signaling recovered from received packets and transmitted out of the TDMoP
block on the TDMn_TSIG signals. See section 10.6.5.2 for more details. When Rx line CAS bits change, an
interrupt is generated. The Rx_CAS_change registers in the Interrupt Controller indicate which timeslots have
changed CAS bits.
In the register descriptions in this section, the index port indicates port number: 1-8 for DS34S108, 1-4 for
DS34S104, 1-2 for DS34S102, 1 only for DS34S101. The index ts indicates timeslot number: 0 to 31.
Table 11-11. Receive Line CAS Registers
Addr
Offset
Register Name Description Page
Port 1
0x000
Rx_Line_CAS_TS0
CAS signaling for timeslot 0 for Port 1
136
0x000+ts*4
Rx_Line_CAS_TS[ts]
CAS signaling for timeslot ts for Port 1
136
0x07C
Rx_Line_CAS_TS31
CAS signaling for timeslot 31 for Port 1
136
Port 2
0x080
Rx_Line_CAS_TS0
CAS signaling for timeslot 0 for Port 2
136
0x080+ts*4
Rx_Line_CAS_TS[ts]
CAS signaling for timeslot ts for Port 2
136
0x0FC
Rx_Line_CAS_TS31
CAS signaling for timeslot 31 for Port 2
136
Port 3
0x100
Rx_Line_CAS_TS0
CAS signaling for timeslot 0 for Port 3
136
0x100+ts*4
Rx_Line_CAS_TS[ts]
CAS signaling for timeslot ts for Port 3
136
0x17C
Rx_Line_CAS_TS31
CAS signaling for timeslot 31 for Port 3
136
Port 4
0x180
Rx_Line_CAS_TS0
CAS signaling for timeslot 0 for Port 4
136
0x180+ts*4
Rx_Line_CAS_TS[ts]
CAS signaling for timeslot ts for Port 4
136
0x1FC
Rx_Line_CAS_TS31
CAS signaling for timeslot 31 for Port 4
136
Port 5
0x200
Rx_Line_CAS_TS0
CAS signaling for timeslot 0 for Port 5
136
0x200+ts*4
Rx_Line_CAS_TS[ts]
CAS signaling for timeslot ts for Port 5
136
0x27C
Rx_Line_CAS_TS31
CAS signaling for timeslot 31 for Port 5
136
Port 6
0x280
Rx_Line_CAS_TS0
CAS signaling for timeslot 0 for Port 6
136
0x280+ts*4
Rx_Line_CAS_TS[ts]
CAS signaling for timeslot ts for Port 6
136
0x2FC
Rx_Line_CAS_TS31
CAS signaling for timeslot 31 for Port 6
136
Port 7
0x300
Rx_Line_CAS_TS0
CAS signaling for timeslot 0 for Port 7
136
0x300+ts*4
Rx_Line_CAS_TS[ts]
CAS signaling for timeslot ts for Port 7
136
0x37C
Rx_Line_CAS_TS31
CAS signaling for timeslot 31 for Port 7
136
Port 8
0x380
Rx_Line_CAS_TS0
CAS signaling for timeslot 0 for Port 8
136
0x380+ts*4
Rx_Line_CAS_TS[ts]
CAS signaling for timeslot ts for Port 8
136
0x3FC
Rx_Line_CAS_TS31
CAS signaling for timeslot 31 for Port 8
136
Rx_Line_CAS 0x000+(port-1)*0x80+ts*4
Bits Data Element Name R/W
Reset
Value
Description
[31:4]
Reserved
-
0x0
Must be set to zero
[3:0]
Rx_CAS
RO
None
CAS signaling (ABCD) towards TDMn_TSIG